參數(shù)資料
型號: ISP1760
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: 高速嵌入式應用的通用串行總線主控制器
文件頁數(shù): 50/105頁
文件大?。?/td> 449K
代理商: ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
50 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
8.4 Interrupt registers
8.4.1
Interrupt register (R/W: 0310h)
The bits of this register indicate the interrupt source, defining the events that determined
the INT generation. Clearing the bits that were set because of the events listed is done by
writing back logic 1 to the respective position. All bits must be reset before enabling new
interrupt events. These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN
in the HW Mode Control register.
Table 54
shows the bit allocation of the Interrupt register.
[1]
The reserved bits should always be written with the reset value.
Table 54:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Interrupt register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
ISO_IRQ
0
R/W
1
ATL_IRQ
0
R/W
0
SOFITLINT
0
0
0
0
0
0
R/W
7
R/W
6
CLK
READY
0
R/W
R/W
5
R/W
4
R/W
3
DMA
EOTINT
0
R/W
R/W
2
INT_IRQ
HC_SUSP
reserved
[1]
reserved
[1]
Reset
Access
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 55:
Bit
31 to 10
9
Interrupt register: bit description
Symbol
Description
-
reserved; write logic 0
ISO_IRQ
ISO IRQ
: Indicates that an IRQ was asserted because an ISO PTD was
completed, or the PTDs corresponding to the bits set in the ISO IRQ
Mask AND or ISO IRQ Mask OR register bits combination were
completed.
0 —
No IRQ assertion determined by the completion of ISO PTDs
1 —
IRQ asserted because of completing ISO PTDs.
For details, see
Section 7.4
.
ATL_IRQ
ATL IRQ
: Indicates that an IRQ was asserted because an ATL PTD was
completed, or the PTDs corresponding to the bits set in the ATL IRQ
Mask AND or ATL IRQ Mask OR register bits combination were
completed.
0 —
No IRQ assertion determined by the completion of ATL PTDs
1 —
IRQ asserted because of completing ATL PTD.
For details, see
Section 7.4
.
8
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