參數(shù)資料
型號: ISP1760
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: 高速嵌入式應(yīng)用的通用串行總線主控制器
文件頁數(shù): 40/105頁
文件大小: 449K
代理商: ISP1760
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
40 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
[1]
The reserved bits should always be written with the reset value.
Bit
Symbol
7
6
5
4
3
2
1
0
reserved
DACK_
POL
0
R/W
DREQ_
POL
0
R/W
reserved
[1]
INTR_POL
INTR_
LEVEL
0
R/W
GLOBAL_
INTR_EN
0
R/W
Reset
Access
0
0
0
0
R/W
R/W
R/W
R/W
Table 34:
Bit
31
HW Mode Control register: bit description
Symbol
Description
ALL_ATX_
RESET
1 —
Enable reset, then write back logic 0
0 —
No reset.
-
reserved; write logic 0
ANA_DIGI_OC
Analog Digital Overcurrent
: This bit selects analog or digital
overcurrent detection on pins OC1_N, OC2_N and OC3_N.
0 —
Digital overcurrent
1 —
Analog overcurrent.
-
reserved; write logic 0
DATA_BUS_
WIDTH
0 —
defines a 16-bit data bus width
1 —
sets a 32-bit data bus width.
-
reserved; write logic 0
DACK_POL
DACK Polarity
:
1 —
indicates that the DACK input is active HIGH
0 —
indicates active LOW.
DREQ_POL
DREQ Polarity
:
1 —
indicates that the DREQ output is active HIGH
0 —
indicates active LOW.
-
reserved; write logic 0
INTR_POL
Interrupt Polarity
:
0 —
active LOW
1 —
active HIGH.
INTR_LEVEL
Interrupt Level
:
0 —
INT level triggered
1 —
INT is edge triggered. A pulse of certain width is generated.
GLOBAL_INTR
_EN
IRQ signal assertion.
0 —
IRQ assertion is disabled. IRQ will never be asserted,
regardless of other settings or IRQ events.
1 —
IRQ assertion is enabled. IRQ will be asserted according to the
Interrupt Enable register, and events setting and occurrence.
All ATX Reset
: For debugging purposes (not used normally).
30 to 16
15
14 to 9
8
Data Bus Width
:
7
6
5
4 to 3
2
1
0
Global Interrupt Enable
: This bit must be set to logic 1 to enable the
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