
IBM038329NL6B
IBM038329NP6B
256K x 32 Synchronous Graphics RAM
03K4292.E35604
Revised 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 66
Signal Descriptions
Name
I/O
Function
A
0
-A
8
, BA (A
9
)
I
Address bits A
0
-A
8
are row addresses when Active command is activated.
Address bits A
0
-A
7
are column addresses when CAS is active.
Address bit A
8
, when CAS is active, enables/disables Auto Precharge.
Address bit BA (A
9
) selects which of the two memory banks is to be used.
CAS
I
CAS is part of the input command to the SGRAM. SeeTtruth Table for details.
CKE
I
Clock Enable disables the clock internally, thus allowing data to remain on the output for several
CLK cycles. Clock Enable is also used as part of the input command to specify Self Refresh.
CLK
I
CLK is driven by the system clock. All SGRAM input signals are sampled on the positive edge of
CLK. The CLK also increments the internal burst counter and controls the output registers.
CS
I
Chip Select indicates that the command on the input lines is for this device. If CS is high, the input
command(s) will be ignored.
DQ
0
-DQ
31
I/O
Data Input/Output lines transfer data between the memory array and the system bus. These are
also input mask bits for Write-per-Bit. When Block Write is activated, DQs provide column address
mask.
DQM
0
-DQM
3
I
During Read, DQM=1 turns off the output buffers.
During Write, DQM=1 prevents a write to the current memory location.
DQM
0
corresponds to the lowest byte (DQ
0
-DQ
7
).
DQM
1
corresponds to DQ
8-15
.
DQM
2
corresponds to DQ
16-23
.
DQM
3
corresponds to DQ
24-31
.
RAS
I
RAS is part of the input command to the SGRAM. See Function Truth Table for details.
WE
I
Write Enable is part of the input command. See Function Truth Table for details.