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| 型號： | IBM038329NP6B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動態(tài)RAM（帶內(nèi)置的圖形性能）) |
| 中文描述： | 256K × 32同步圖形RAM（256K × 32位高性能800萬的CMOS同步動態(tài)隨機存儲器（帶內(nèi)置的圖形性能）） |
| 文件頁數(shù)： | 14/66頁 |
| 文件大?。?/td> | 952K |
| 代理商： | IBM038329NP6B |
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IBM038329NL6B
IBM038329NP6B
256K x 32 Synchronous Graphics RAM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 66
03K4292.E35604
Revised 3/98
Register Definition
The following pages describe the Mode Register and Special Mode Register functions.
Mode Register
The Mode Register is used to define burst length, burst type, CAS Latency, and an operating mode as shown
in Mode Register Functions on page 16. The mode register is programmed via the Load Mode Register com-
mand and will retain the stored information until it is programmed again or the device loses power.The Mode
Register must be loaded when both banks are idle and the controller must wait the specified time before initi-
ating the subsequent command. Violating either of these requirements may result in unknown operation.
Burst Length
Read and Write operations to the SGRAM are burst oriented, with the burst length being programmable, as
shown in Mode Register Functions on page 16. The burst length determines the maximum number of column
locations that can be accessed for a given Read or Write command. Burst lengths of 1, 2, 4, or 8 locations are
available for both the sequential and the interleaved burst types and a Full Page Burst is available for the
sequential type. The Full Page Burst is used in conjunction with the Burst Terminate command to generate
arbitrary burst lengths.
When a Read or Write command is issued, a block of columns equal to the burst length is selected. The block
is defined by address bits A
7
-A
1
when the burst length is set to 2, by A
7
-A
2
for burst length is set to 4 and by
A
7
-A
3
when the burst length is set to 8. The lower order bit(s) are used to select the starting location within
the block. The burst will wrap within the block if a boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved and the type is
selected based on the setting of the BT bit in the Mode Register. If BT is set to “0”, the burst type is sequen-
tial; if BT is “1”, the burst type is interleaved.
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