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參數(shù)資料
| 型號(hào)： | IBM038329NP6B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動(dòng)態(tài)RAM（帶內(nèi)置的圖形性能）) |
| 中文描述： | 256K × 32同步圖形RAM（256K × 32位高性能800萬的CMOS同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶內(nèi)置的圖形性能）） |
| 文件頁數(shù)： | 11/66頁 |
| 文件大小： | 952K |
| 代理商： | IBM038329NP6B |
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IBM038329NL6B
IBM038329NP6B
256K x 32 Synchronous Graphics RAM
03K4292.E35604
Revised 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 66
Refreshing
H
X
X
X
X
X
INHBT
NOP
→
Enter Idle after t
RC
L
H
H
X
X
X
NOP
NOP
→
Enter Idle after t
RC
L
H
H
L
X
X
BST
NOP
→
Enter Idle after t
RC
L
H
L
H
X
BA, CA, AP
RD/RDA
ILLEGAL
L
H
L
L
L
BA, CA, AP
WR/WRA
ILLEGAL
L
H
L
L
H
BA, CA, AP
BW/BWA
ILLEGAL
L
L
H
H
L
BA, RA
ACT
ILLEGAL
L
L
H
H
H
BA, RA
ACTM
ILLEGAL
L
L
H
L
X
BA, PA
PRE/PREAL
ILLEGAL
L
L
L
H
X
X
REF/SREF
ILLEGAL
L
L
L
L
L
Op-Code
LMR
ILLEGAL
L
L
L
L
H
OP-CODE
LSMR
ILLEGAL
Mode
Register
Accessing
H
X
X
X
X
X
INHBT
NOP
→
Enter Idle after two clocks
L
H
H
X
X
X
NOP
NOP
→
Enter Idle after two clocks
L
H
H
L
X
X
BST
NOP
→
Enter Idle after two clocks
L
H
L
H
X
BA, CA, AP
RD/RDA
ILLEGAL
L
H
L
L
L
BA, CA, AP
WR/WRA
ILLEGAL
L
H
L
L
H
BA, CA, AP
BW/BWA
ILLEGAL
L
L
H
H
L
BA, RA
ACT
ILLEGAL
L
L
H
H
H
BA, RA
ACTM
ILLEGAL
L
L
H
L
X
BA, PA
PRE/PREAL
ILLEGAL
L
L
L
H
X
X
REF/SREF
ILLEGAL
L
L
L
L
L
Op-Code
LMR
ILLEGAL
L
L
L
L
H
Op-Code
LSMR
ILLEGAL
Operative Command Table (Part 6 of 6)
Current State
CS
RAS CAS
WE
DSF
Add
Command
Action
Notes
ABBREVIATIONS: H = High level; L = Low level; X = Don’t care (high or low); V = Valid data input
NOTE: All entries assume that CKE was active (High level) during the preceding clock cycle.
1. Illegal to bank specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that
bank.
2. Must satisfy bus contention, bus turnaround, and/or write recovery requirements.
3. If both banks are idle and CKE is inactive (Low level), the device will enter Power Down Mode. All input buffers except CKE will be
disabled.
4. If both banks are idle and CKE is inactive (Low level), the device will enter Self Refresh Mode. All input buffers except CKE will be
disabled.
5. Illegal if t
RRD
is not satisfied.
6. Illegal if t
RAS
is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must mask preceding data which don’t satisfy t
DPL
.
9. Illegal if t
RCD
is not satisfied.
RA = Row Address (A0 - A8)
NOP = No Operation Command
BA = Bank Address (A9)
CA = Column Address (A0 - A7)
PA = Precharge All (A8)
AP = Auto Precharge (A8)
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