參數(shù)資料
型號： IBM038329NP6B
廠商： IBM Microeletronics
英文描述： 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動(dòng)態(tài)RAM（帶內(nèi)置的圖形性能）)
中文描述： 256K × 32同步圖形RAM（256K × 32位高性能800萬的CMOS同步動(dòng)態(tài)隨機(jī)存儲器（帶內(nèi)置的圖形性能））
文件頁數(shù)： 15/66頁
文件大?。?/td> 952K
代理商： IBM038329NP6B
IBM038329NL6B
IBM038329NP6B
256K x 32 Synchronous Graphics RAM
03K4292.E35604
Revised 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 66
CAS Latency
The CAS Latency is the delay in clock cycles between the registration of a Read command and the availabil-
ity of the first piece of output data. The latency can be set to 1, 2, or 3 clocks. If a Read command is regis-
tered at clock edge n and the Read Latency is 2 clocks, the data will be available by clock edge n+2. The DQs
will start driving as a result of the clock edge one cycle earlier (n+1) and provided the relevant access times
are met, the data will be valid by clock edge n+2.
Operation Mode
In normal operation, the M
7
-M
9
bits of Mode Register (MR) are set to “0”. The programmed burst length
applies to both read and write bursts. If Bit M
7
is set equal to “1”, two Color Registers are specified. Test
modes and reserved states should not be used because unknown operation or incompatibility with future ver-
sions may result.
Load Special Mode Register (LSMR)
The Load Special Mode Register command is used to load the Mask and Color Registers, which are used in
Block Write and Masked Write cycles.The data to be written to either the Color Registers or the Mask Regis-
ter is applied to the DQs and the control information is applied to the address inputs. During a LSMR cycle, if
the address bit A
6
is “1” and all other address inputs are “0”,Color Register 0 will be loaded with the data on
the DQs. If address bits A
6
and A
7
are both set to “1” and Mode Register bit M
7
was already set to “1”, Color
Register 1 will be loaded with the data on the DQs. This color data is used for Block Write cycles. Similarly,
when input A
5
is “1” and all other address inputs are “0” during a LSMR cycle, the Mask Register will be
loaded with the data on the DQs.
Caution:
Never set bit A
5
to “1” when A
6
and/or A
7
are set to “1” in the same Load Special Mode Register cycle to
avoid unknown operation. (See Special Mode Register Functions on page 18.)
Color Registers
Two Color Registers (Color Register 0 and Color Register 1) are available in the devices. (See Block Write
Illustration on page 19.) Each Color Register is a 32-bit register which supplies data during Block Write
cycles. The Color Register is loaded via a Load Special Mode Register command, as shown in the Initialize
and Load Mode Register Operation on page 28, and will retain data until loaded again with new data or until
power is removed from the SGRAM.
Mask Register
The Mask Register (or the Write-per-Bit Mask Register) is a 32-bit register which acts as a per-bit mask dur-
ing Masked Write and Masked Block Write cycles. The Mask Register is loaded via the Load Special Mode
Register command and will retain data until loaded again or until power is removed from the SGRAM.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM038329NQ6A-7R5 制造商:IBM 功能描述:
IBM041812PQKB10 制造商:IBM 功能描述:*
IBM041812PQKB11 制造商:IBM 功能描述:*
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