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參數(shù)資料
| 型號(hào)： | IBM038329NP6B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256K x 32 Synchronous Graphics RAM(256K x 32 高性能8M位CMOS同步動(dòng)態(tài)RAM（帶內(nèi)置的圖形性能）) |
| 中文描述： | 256K × 32同步圖形RAM（256K × 32位高性能800萬(wàn)的CMOS同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶內(nèi)置的圖形性能）） |
| 文件頁(yè)數(shù)： | 27/66頁(yè) |
| 文件大?。?/td> | 952K |
| 代理商： | IBM038329NP6B |
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IBM038329NL6B
IBM038329NP6B
256K x 32 Synchronous Graphics RAM
03K4292.E35604
Revised 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 27 of 66
Detailed Operation
Initialization and Load Mode Register
The SGRAM must be initialized at power up time to prevent undefined operations. The Initialize and Load
Mode Register Operation on page 28 shows this process in detail. The next step is to load the mode register
to program the burst length and burst type. The Load Mode Register and Special Mode Register functions
have been described earlier.
The initialization of the device and loading of the Mode Register is shown in Initialize and Load Mode Register
Operation on page 28. If the device is not initialized prior to issuing a command, it may result in undefined
operation. The Mode Register should be loaded to let the device know burst type, length of burst, CAS
latency, and sequence and number of color registers to be used.
Auto Refresh (REF)
This mode is similar to CBR used in conventional DRAMs to refresh the DRAM rows.
This command is essential to refresh the volatile DRAM cells every 16ms. The device could be refreshed by
issuing 1024 Auto Refresh cycles every 16ms or these refresh cycles could be interleaved between various
operations as long as each DRAM cell is refreshed every 16ms or less.
Logic Table for Auto Refresh Command Cycle
Mnemonic
CKE
CS
RAS
CAS
WE
DSF
DQM
BA (A9)
A8
A7-A0
REF
H
L
L
L
H
L
X
X
X
X
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