參數(shù)資料
型號(hào): HYB18T256324F-22
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256-Mbit GDDR3 DRAM [600MHz]
中文描述: 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁數(shù): 56/80頁
文件大?。?/td> 2026K
代理商: HYB18T256324F-22
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
56
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
Figure 40
DTERDIS followed by DTERDIS
1. At least 1NOP is required between 2 DTERDIS commands. This correspond to a Read to Read transistion on
the other memory in a 2 rank system.
2. CAS Latency 5 is used as an example.
3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of (BL/2
+ 2 ) clocks
4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command
corresponds to a Read command applied to the second Graphics DRAM in a 2 rank system. In this case,
RDQS would be driven by the second Graphics DRAM.
!DDR
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$1S 4ERMINATIONS OFF
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