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| 型號(hào)： | HYB18T256324F-22 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit GDDR3 DRAM [600MHz] |
| 中文描述： | 256兆GDDR3顯示內(nèi)存[600MHz的] |
| 文件頁(yè)數(shù)： | 43/80頁(yè) |
| 文件大?。?/td> | 2026K |
| 代理商： | HYB18T256324F-22 |
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HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
43
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.7.6
Write followed by DTERDIS
Figure 26
Write Command followed by DTERDIS
1. Write shown with nominal value of
t
DQSS.
2. WDQS can only transition when data is applied at the chip input and during pre- and postambles
3. A margin of one clock has been introduced in order to make sure that the data termination are still on when
the last Write data reaches the memory.
4. The minimum distance between Write and DTERDIS is (WL -CL + 4) clocks and always bigger than or equal
to 1. For (CL=6 / WL=2) and (CL=7 / WL=3) as well as for (CL=7 / WL=2) the minimum distance between Write
and DTERDIS is set to 1 clock. Please refer to table below:
Table 24
WL \ CL
2
3
4
WL / CL
5
1
2
3
6
1
1
2
7
1
1
1
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