參數(shù)資料
型號(hào)： HYB18T256324F-22
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁數(shù)： 47/80頁
文件大?。?/td> 2026K
代理商： HYB18T256324F-22
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
47
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
Figure 30
Basic Read Burst Timing
1. The GDDR3 SGRAM switches off the DQ terminations one cycle before data appears on the busand drives
the data bus HIGH.
2. The GDDR3 SGRAM drives the data bus HIGH one cycle after the last data driven on the bus before switching
the termination on again.
1.
t
CCD
is either for gapless consecutive reads or gapless consecutive writes.
2. Please round up
t
RTW
to the next integer of
t
CK
.
3.
t
HP
is the minimum of
t
CL
and
t
CH
4. Timing parameters defined with controller terminations on.
Table 25
Parameter
READ Timing Parameters for –1.6, –2.0 and –2.2 speed sorts
Symbol
Limit Values
–2.0
min
2
Unit
Note
–1.6
–2.2
min
2
max
—
max
—
min
2
max
—
CAS (a) to CAS (b) Command period
t
CCD
t
RTW
t
CK
t
CK
1
2
Read to Write command delay
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock
Read Preamble
t
RTW
(min)= (CL+4-WL)
t
AC
t
RPRE
t
RPST
–0.4
0.75
0.4
1.25
–0.4
0.75
0.4
1.25
–0.45
0.75
0.45
1.25
ns
t
CK
t
CK
4
Read Postamble
Data-out high impedance time from CLK
t
HZ
Data-out low impedance time from CLK
t
LZ
RDQS edge to Clock edge skew
RDQS edge to output data edge skew
Data hold skew factor
Data output hold time from RDQS
Minimum clock half period
0.75
t
ACmin
t
ACmin
–0.4
—
0
t
HP
–
t
QHS
0.45
1.25
t
ACmax
t
ACmin
t
ACmax
t
ACmin
0.4
0.225 —
0.225 0
0.75
1.25
t
ACmax
t
ACmin
t
ACmax
t
ACmin
0.4
0.225 —
0.225 0
0.75
1.25
t
ACmax
n
s
t
ACmax
n
s
0.45
0.25
0.25
4
4
4
4
4
4
3
t
DQSCK
t
DQSQ
t
QHS
t
QH
t
HP
–0.4
–0.45
ns
ns
ns
ns
t
CK
t
HP
–
t
QHS
0.45
t
HP
–
t
QHS
0.45
—
—
—
T
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