參數(shù)資料
型號(hào)： HYB18T256324F-22
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁(yè)數(shù)： 25/80頁(yè)
文件大小： 2026K
代理商： HYB18T256324F-22
10
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
25
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.3.2
Self Calibration for Driver and Termination
Figure 7
Termination update keep out time after Autorefresh command
To guarantee optimum driver impedance after power-up, the GDDR3 SGRAM needs 350 cycles after the clock is
applied and stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 350
cycles, but optimal output impedance will not be guaranteed.
The GDDR3 Graphics RAM proceeds in the following manner for Self Calibration :
The PMOS device is calibrated against the external ZQ resistor value (
Figure 8
). First one PMOS leg is calibrated
against ZQ. The number of legs used for the terminators ( DQ and ADD/CMD) and the PMOS driver is represented
in
Table 14
. Next, one NMOS leg is calibrated against the already calibrated PMOS leg. The NMOS driver uses
6 NMOS legs.
Note:EMRS[3:2] = 00 disables the ADD and CMD terminations as well.
Table 13
Termination update Keep Out time
Parameter
Symbol
Limit Values
–2.0
min
10
Unit
Notes
–1.6
–2.2
min
max
—
max
—
min
10
max
—
Termination update Keep Out time
t
KO
ns
Table 14
Number of Legs used for Terminator and Driver Self Calibration
Termination
Number of Legs Notes
CKE (at RES)
0
1
EMRS[3:2]
00
10
11
Terminator
ADD / CMD
ZQ/2
ZQ
2
1
DQ
Disabled
ZQ/4
ZQ/2
ZQ/6
ZQ/6
0
4
2
6
6
1
Driver
PMOS
NMOS
#,+
#,+
$ONgT#ARE
T
+/
#OM
!2&!UTOREFRESH
!2&
!DD
$1
+EEP/UTTIME
./0
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