參數(shù)資料
型號(hào)： HYB18T256324F-22
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256-Mbit GDDR3 DRAM [600MHz]
中文描述： 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁數(shù)： 53/80頁
文件大?。?/td> 2026K
代理商： HYB18T256324F-22
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Functional Description
Data Sheet
53
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
3.8.5
Read followed by Write
Figure 36
Read followed by Write
1. Shown with nominal
t
AC
,
t
DQSQ
and
t
DQSS
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
4. WDQS can only transition when data is applied at the chip input and during pre- and postambles
5. The Write command may be either on the same bank or on another bank
#,+
#,+
#OM
!DDR
$ONgT #ARE
2$
$%3
$%3
$%3
$ %3
" #R
$%3
$%3
2$
$%3
$%3
$%3
$ %3
" #R
$%3
$%3
$%3
#!3 LATENCY
T
24 7
7RITE LATENCY
7$13
2$13
$1
#!3 LATENCY
T
24 7
7RITE LATENCY
7$13
2$13
$1
$ R
$ R
$ R
$ R
$%3
72
" #W
$ W
$ W
$ W
$ W
$ R
$ R
$ R
$ R
$ W
$ W
$ W
$%3
" #W
72
$XR
$XW
2%!$ $A TA FROM " #
72)4% $A TA FROM " #
#OM
!DDR
#OMMAND
!DDRESS " #
" #W
2$
72
$%3
"ANK #OLUMN ADDRESS FOR 72 4%
2%!$
72)4%
$ESELECT
" #R
"ANK #O LUMN ADDRESS FOR 2%!$
$1S 4ERMINATIONS OFF
2$13 .OT DRIVEN
$%3
$%3
$%3
$%3
$%3
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