參數(shù)資料
型號: HYB18T256324F-22
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256-Mbit GDDR3 DRAM [600MHz]
中文描述: 256兆GDDR3顯示內(nèi)存[600MHz的]
文件頁數(shù): 13/80頁
文件大?。?/td> 2026K
代理商: HYB18T256324F-22
HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Data Sheet
13
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
RES
Input
Reset pin:
The RES pin is a
V
DDQ
CMOS input. RES is not internally terminated. The
LOW to HIGH transition of the Reset signal is used to latch the CKE value during Power
On in order to set the value of the termination resistors of the address and command
inputs. When RES is LOW, all terminations are switched off. The LOW to HIGH transition
of the RES signal must occur at the beginning of the power up sequence in order to insure
functionnality.
Supply
Voltage Reference:
V
ref
is the reference voltage input.
Supply
Power Supply:
Power and Ground for the internal logic.
Supply
I/O Power Supply:
Isolated Power and Ground for the output buffers to provide improved
noise immunity.
-
Please do not connect No Connect and Reserved for Future Use balls.
V
ref
V
DD
,
V
SS
V
DDQ
,
V
SSQ
NC, RFU
Table 3
Ball
Ball description
Type
Detailed Function
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