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參數(shù)資料
| 型號： | HYB18T256324F-22 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256-Mbit GDDR3 DRAM [600MHz] |
| 中文描述： | 256兆GDDR3顯示內(nèi)存[600MHz的] |
| 文件頁數(shù)： | 16/80頁 |
| 文件大?。?/td> | 2026K |
| 代理商： | HYB18T256324F-22 |
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HYB18T256324F–[16/20/22]
256-Mbit DDR SGRAM
Pin Configuration
Data Sheet
16
Rev. 1.11, 04-2005
10292004-DOXT-FS0U
2.3.2
Description of Commands
Table 5
Command
DESEL
Description of Commands
Description
The DESEL function prevents new commands from being executed by the Graphics SDRAM. The
Graphics SDRAM is effectively deselected. Operations in progress are not affected.
The NOP command is used to perform a no operation to the Graphics SDRAM, which is selected
(CS is LOW). This prevents unwanted commands from being registered during idle or wait states.
Operations already in progress are not affected.
The Mode Register is loaded via address inputs A0 - A11. For more details see sections
Chapter 3.5
. The MRS command can only be issued when all banks are idle and no bursts are in
progress. A subsequent executable command cannot be issued until t
MRD
is met.
The Extended Mode Register is loaded via address inputs A0 - A11. For more details see section
Chapter 3.4
. The EMRS command can only be issued when all banks are idle and no bursts are in
progress. A subsequent executable command cannot be issued until t
MRD
is met.
The ACT command is used to open (or activate) a row in a particular bank for a subsequent access.
The value on the BA0 and BA1 inputs selects the bank, and the address provided in inputs A0 - A11
selects the row. This row remains active (or open) for accesses until a precharge (PRE, RD/A, or
WR/A command) is issued to that bank. A precharge must be issued before opening a different row
in the same bank.
The RD command is used to initiate a burst read access to an active row. The value on the BA0 and
BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The row will remain open for subsequent accesses. For RD commands the value on A8 is
set LOW.
The RD/A command is used to initiate a burst read access to an active row. The value on the BA0
and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end
of the read burst. The same individual-bank precharge function is performed like it is described for
the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage
within the burst. The user must not issue a new ACT command to the same bank until the precharge
time (t
RP
) is completed. This time is determined as if an explicit PRE command was issued at the
earliest possible time as described in section
Chapter 3.10
.
The WR command is used to initiate a burst write access to an active row. The value on the BA0
and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The row will remain open for subsequent accesses. For WR commands the value on A8 is
set LOW.
Input data appearing on the DQs is written to the memory array depending on the value on the DM
input appearing coincident with the data. If a given DM signal is registered LOW, the corresponding
data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a write will not be executed for that byte / column location.
The WR/A command is used to initiate a burst write access to an active row. The value on the BA0
and BA1 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column
location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end
of the write burst. The same individual-bank precharge function is performed which is described for
the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage
within the burst. The user is not allowed to issue a new ACT to the same bank until the precharge
time (t
RP
) is completed. This time is determined as if an explicit PRE command was issued at the
earliest possible time as described in section
Chapter 3.7
.
Input data appearing on the DQs is written to the memory array depending on the DM input logic
level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding
data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a write will not be executed to that byte / column location.
NOP
MRS
EMRS
ACT
RD
RD/A
WR
WR/A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
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