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| 型號(hào)： | HMT351V7BFR8C-H9 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁(yè)數(shù)： | 49/61頁(yè) |
| 文件大?。?/td> | 1050K |
| 代理商： | HMT351V7BFR8C-H9 |
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Rev. 0.1 / Feb. 2010
53
Table 10 - IDD7 Measurement-Loop Patterna)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
CK,
CK
CKE
Sub-Loop
Cyc
le
Number
C
o
mmand
CS
RAS
CAS
WE
OD
T
BA[
2
:0]
A[1
5
:1
1]
A[1
0
]
A[9:7]
A[6:3]
A[2
:0]
Datab)
to
ggl
ing
St
atic
Hig
h
00
ACT
0
1
0
00
0
-
1
RDA
0
1
0
1
0
00
1
0
00000000
2D
1
0
00
0
-
...
repeat above D Command until nRRD - 1
1
nRRD
ACT
0
1
0
1
00
0
F
0
-
nRRD+1
RDA
0
1
0
1
0
1
00
1
0
F
0
00110011
nRRD+2
D
1
0
1
00
0
F
0
-
...
repeat above D Command until 2* nRRD - 1
2
2*nRRD
repeat Sub-Loop 0, but BA[2:0] = 2
3
3*nRRD
repeat Sub-Loop 1, but BA[2:0] = 3
4
4*nRRD
D1
0
3
00
0
F
0
-
Assert and repeat above D Command until nFAW - 1, if necessary
5
nFAW
repeat Sub-Loop 0, but BA[2:0] = 4
6
nFAW+nRRD
repeat Sub-Loop 1, but BA[2:0] = 5
7
nFAW+2*nRRD
repeat Sub-Loop 0, but BA[2:0] = 6
8
nFAW+3*nRRD
repeat Sub-Loop 1, but BA[2:0] = 7
9
nFAW+4*nRRD
D1
0
7
00
0
F
0
-
Assert and repeat above D Command until 2* nFAW - 1, if necessary
10
2*nFAW+0
ACT
0
1
0
00
0
F
0
-
2*nFAW+1
RDA
0
1
0
1
0
00
1
0
F
0
00110011
2&nFAW+2
D1
0
00
0
F
0
-
Repeat above D Command until 2* nFAW + nRRD - 1
11
2*nFAW+nRRD
ACT
0
1
0
1
00
0
-
2*nFAW+nRRD+1
RDA
0
1
0
1
0
1
00
1
0
00000000
2&nFAW+nRRD+2
D1
0
1
00
0
-
Repeat above D Command until 2* nFAW + 2* nRRD - 1
12
2*nFAW+2*nRRD
repeat Sub-Loop 10, but BA[2:0] = 2
13
2*nFAW+3*nRRD
repeat Sub-Loop 11, but BA[2:0] = 3
14
2*nFAW+4*nRRD
D1
0
3
00
0
-
Assert and repeat above D Command until 3* nFAW - 1, if necessary
15
3*nFAW
repeat Sub-Loop 10, but BA[2:0] = 4
16
3*nFAW+nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
17
3*nFAW+2*nRRD
repeat Sub-Loop 10, but BA[2:0] = 6
18
3*nFAW+3*nRRD
repeat Sub-Loop 11, but BA[2:0] = 7
19
3*nFAW+4*nRRD
D1
0
7
00
0
-
Assert and repeat above D Command until 4* nFAW - 1, if necessary
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| HMT351V7BMR4C-G7 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
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| HMT351V7BMR8C-H9 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
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