參數(shù)資料
型號(hào): HMT351V7BFR8C-H9
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: DDR DRAM MODULE, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 47/61頁
文件大?。?/td> 1050K
代理商: HMT351V7BFR8C-H9
Rev. 0.1 / Feb. 2010
51
Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Patterna)
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
CK,
CK
CKE
Sub
-Loop
Cy
cle
Number
Command
CS
RAS
CAS
WE
OD
T
BA[
2
:0]
A[1
5
:1
1]
A[1
0
]
A
[9:7]
A
[6:3]
A[2
:0]
Datab)
toggling
Sta
tic
Hi
gh
0
RD
0
1
0
1
0
00
0
00000000
1D
1
0
00
0
-
2,3
D,D
11
1
0
00
0
-
4
RD
0
1
0
1
0
00
0
F
0
00110011
5D
1
0
00
0
F
0
-
6,7
D,D
11
1
0
00
0
F
0
-
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
CK,
CK
CKE
Su
b
-Lo
op
Cycle
Nu
mb
er
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[1
5
:1
1]
A[10]
A[9:7]
A[6:3]
A[2
:0]
Datab)
toggling
Sta
tic
Hi
gh
0
WR
0
1
0
1
0
00
0
00000000
1D
1
0
1
0
00
0
-
2,3
D,D
11
1
0
00
0
-
4
WR
0
1
0
1
0
00
0
F
0
00110011
5D
1
0
1
0
00
0
F
0
-
6,7
D,D
11
1
0
00
0
F
0
-
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
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