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參數(shù)資料
| 型號(hào)： | HMT351V7BFR8C-H9 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 22/61頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | HMT351V7BFR8C-H9 |
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Rev. 0.1 / Feb. 2010
29
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” on page 137 in “DDR3 Device Operation” for sin-
gle-ended slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” on page 144 in “DDR3 Device Operation” for single-
ended slew rate definition for data signals.
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table
and figure below.
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Differential Input Slew Rate Definition
Description
Measured
Defined by
Min
Max
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
VILdiffmax
VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
VIHdiffmin
VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
Delta
TFdiff
Delta
TRdiff
vIHdiffmin
vILdiffmax
0
Differential
Inp
ut
Voltag
e(i.e.
DQS-DQS;
CK-CK
)
Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMT351V7BMR4C-G7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7BMR4C-H9 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7BMR8C-G7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7BMR8C-H9 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7CFR4A | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:DDR3L SDRAM VLP Registered DIMM Based on 2Gb C-die |
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