參數(shù)資料
型號: HMT351V7BFR8C-H9
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: DDR DRAM MODULE, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 32/61頁
文件大?。?/td> 1050K
代理商: HMT351V7BFR8C-H9
Rev. 0.1 / Feb. 2010
38
DDR3-1333 Speed Bins
For specific Notes See “Speed Bin Table Notes” on page 39.
Speed Bin
DDR3-1333H
Unit
Note
CL - nRCD - nRP
9-9-9
Parameter
Symbol
min
max
Internal read command
to first data
tAA
13.5
(13.125)8
20
ns
ACT to internal read or
write delay time
tRCD
13.5
(13.125)8
—ns
PRE command period
tRP
13.5
(13.125)8
—ns
ACT to ACT or REF
command period
tRC
49.5
(49.125)8
—ns
ACT to PRE command
period
tRAS
36
9 * tREFI
ns
CL = 5
CWL = 5
tCK(AVG)
Reserved
ns
1,2, 3,4, 6
CWL = 6, 7
tCK(AVG)
Reserved
ns
4
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
ns
1, 2, 3, 6
CWL = 6
tCK(AVG)
Reserved
ns
1, 2, 3, 4, 6
CWL = 7
tCK(AVG)
Reserved
ns
4
CL = 7
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1, 2, 3, 4, 6
Reserved
CWL = 7
tCK(AVG)
Reserved
ns
1, 2, 3, 4
CL = 8
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1, 2, 3, 6
CWL = 7
tCK(AVG)
Reserved
ns
1, 2, 3, 4
CL = 9
CWL = 5, 6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1, 2, 3, 4
CL = 10
CWL = 5, 6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1, 2, 3
Reserved
ns
Supported CL Settings
6, 8, (7), 9, (10)
nCK
Supported CWL Settings
5, 6, 7
nCK
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