參數(shù)資料
型號(hào)： HMT351V7BFR8C-H9
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： DDR DRAM MODULE, DMA240
封裝： ROHS COMPLIANT, DIMM-240
文件頁(yè)數(shù)： 39/61頁(yè)
文件大?。?/td> 1050K
代理商： HMT351V7BFR8C-H9
Rev. 0.1 / Feb. 2010
44
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
DDR3-1066
DDR3-1333
Unit
7-7-7
9-9-9
tCK
1.875
1.5
ns
CL
7
9
nCK
nRCD
79
nCK
nRC
27
33
nCK
nRAS
20
24
nCK
nRP
79
nCK
nFAW
1KB page size
20
nCK
2KB page size
27
30
nCK
nRRD
1KB page size
4
nCK
2KB page size
6
5
nCK
nRFC -512Mb
48
60
nCK
nRFC-1 Gb
59
74
nCK
nRFC- 2 Gb
86
107
nCK
nRFC- 4 Gb
160
200
nCK
nRFC- 8 Gb
187
234
nCK
Symbol
Description
IDD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
IDD1
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
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