參數(shù)資料
型號： HMT351V7BFR8C-H9
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： DDR DRAM MODULE, DMA240
封裝： ROHS COMPLIANT, DIMM-240
文件頁數(shù)： 40/61頁
文件大?。?/td> 1050K
代理商： HMT351V7BFR8C-H9
Rev. 0.1 / Feb. 2010
45
IDD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
IDD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
IDD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow
Exitc)
IDD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 5.
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Symbol
Description
相關(guān)PDF資料
PDF描述
HN4400 NPN EXPITAXIAL SILICON TRANSISTOR
HN5400 PNP Silicon Expitaxial Planar Transistor for general purpose, high voltage amplifier applications
HN5401 PNP Silicon Expitaxial Planar Transistor for general purpose, high voltage amplifier applications
HN546 NPN Silicon Epitaxial Planar Transistor
HN547 NPN Silicon Epitaxial Planar Transistor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HMT351V7BMR4C-G7 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM
HMT351V7BMR4C-H9 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM
HMT351V7BMR8C-G7 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM
HMT351V7BMR8C-H9 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM
HMT351V7CFR4A 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:DDR3L SDRAM VLP Registered DIMM Based on 2Gb C-die
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*