參數(shù)資料
型號: HMT351V7BFR8C-H9
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: DDR DRAM MODULE, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 25/61頁
文件大?。?/td> 1050K
代理商: HMT351V7BFR8C-H9
Rev. 0.1 / Feb. 2010
31
Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below.
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Single Ended Output slew Rate Definition
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Single-ended Output slew Rate Definition
Description
Measured
Defined by
From
To
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC)-VOL(AC)] / DeltaTRse
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC)-VOL(AC)] / DeltaTFse
Output Slew Rate (single-ended)
DDR3-800
DDR3-1066
DDR3-1333
Units
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Single-ended Output Slew Rate
SRQse
2.5
5
2.5
5
2.5
5
V/ns
Delta TFse
Delta TRse
vOH(AC)
vOl(AC)
V
Si
ng
le
En
ded
O
ut
put
V
olt
age(
l.e.
DQ
)
Single Ended Output Slew Rate Definition
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