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| 型號： | HMT351V7BFR8C-H9 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 21/61頁 |
| 文件大小： | 1050K |
| 代理商： | HMT351V7BFR8C-H9 |
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Rev. 0.1 / Feb. 2010
28
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
Vix Definition
Notes:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are
monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential
slew rate of CK - CK is larger than 3 V/ns.
2. Refer to the table “Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU” on page 18
for VSEL and VSEH standard values.
Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
DDR3-800, 1066, 1333
Unit Notes
Min
Max
VIX
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK
-150
150
mV
-175
175
mV
1
VIX
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS
-150
150
mV
VDD
VSS
VDD/2
VIX
CK, DQS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMT351V7BMR4C-G7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7BMR4C-H9 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7BMR8C-G7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7BMR8C-H9 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR3 SDRAM VLP Registered DIMM |
| HMT351V7CFR4A | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:DDR3L SDRAM VLP Registered DIMM Based on 2Gb C-die |
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