參數(shù)資料
型號： HC05PL4GRS
英文描述： 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification
中文描述： 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范
文件頁數(shù)： 79/98頁
文件大小： 1004K
代理商： HC05PL4GRS
April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
INSTRUCTION SET
MOTOROLA
12-11
INC opr
INCA
INCX
INC oprX
INC ,X
JMP opr
JMP opr
JMP oprX
JMP oprX
JMP ,X
JSR opr
JSR opr
JSR oprX
JSR oprX
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA oprX
LDA oprX
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX oprX
LDX oprX
LDX ,X
LSL opr
LSLA
LSLX
LSL oprX
LSL ,X
LSR opr
LSRA
LSRX
LSR oprX
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG oprX
NEG ,X
NOP
Increment Byte
M
←
(M) + 1
A
←
(A) + 1
X
←
(X) + 1
M
←
(M) + 1
M
←
(M) + 1
— —
—
DIR
INH
INH
IX1
IX
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
INH
DIR
INH
INH
IX1
IX
INH
3C
4C
5C
6C
7C
BC
CC
DC
EC
FC
BD
CD
DD
ED
FD
A6
B6
C6
D6
E6
F6
AE
BE
CE
DE
EE
FE
38
48
58
68
78
34
44
54
64
74
42
30
40
50
60
70
9D
dd
ff
5
3
3
6
5
2
3
4
3
2
5
6
7
6
5
2
3
4
5
4
3
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
11
5
3
3
6
5
2
Unconditional Jump
PC
←
Jump Address
— — — — —
dd
hh ll
ee ff
ff
Jump to Subroutine
PC
←
(PC) + n (n = 1, 2, or 3)
Push (PCL); SP
←
(SP) – 1
Push (PCH); SP
←
(SP) – 1
PC
←
Conditional Address
— — — — —
dd
hh ll
ee ff
ff
Load Accumulator
with Memory Byte
A
←
(M)
— —
—
ii
dd
hh ll
ee ff
ff
Load Index Register
with Memory Byte
X
←
(M)
— —
—
ii
dd
hh ll
ee ff
ff
Logical Shift Left
(Same as ASL)
— —
dd
ff
Logical Shift Right
— — 0
dd
ff
Unsigned Multiply
X : A
←
(X)
×
(A)
M
←
–(M) = $00 – (M)
A
←
–(A) = $00 – (A)
X
←
–(X) = $00 – (X)
M
←
–(M) = $00 – (M)
M
←
–(M) = $00 – (M)
0 — — — 0
Negate Byte
(Two’s Complement)
— —
ii
ff
No Operation
— — — — —
Table 12-6. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
A
M
O
O
C
H I N Z C
C
b0
b7
0
b0
b7
C
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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