參數(shù)資料
型號(hào)： HC05PL4GRS
英文描述： 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification
中文描述： 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范
文件頁(yè)數(shù)： 60/98頁(yè)
文件大?。?/td> 1004K
代理商： HC05PL4GRS
GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
9-10
16-BIT PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC05PL4
REV 2.0
TCMPEN - TIMER OUTPUT COMPARE ENABLE
The bit configures port pin PA3 for Timer16 output compare function (TCMP).
At power-on-reset, this bit is cleared, PA3 is a standard I/O port pin, TCMP sig-
nal to PA3 is disabled from Timer16.
1 =
PA3 pin configured as TCMP for timer output compare
0 =
PA3 pin as standard I/O port pin
9.6
TIMER STATUS REGISTER (TSR)
The timer status register (TSR) shown in
Figure 9-12
contains flags for the follow-
ing events:
An active signal on the PA2/TCAP pin transferring the contents of the
timer registers to the input capture registers.
A match between the 16-bit counter and the output compare registers,
transferring the OLVL bit to the TCMP.
An overflow of the timer registers from $FFFF to $0000.
Writing to any of the bits in the TSR has no effect. Reset does not change the
state of any of the flag bits in the TSR.
ICF - INPUT CAPTURE FLAG
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PA2/TCAP pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICRL, $0015) of the input capture
registers. Resets have no effect on ICF.
OCF - OUTPUT COMPARE FLAG
The OCF bit is automatically set when the value of the timer registers matches
the contents of the output compare registers. Clear the OCF bit by reading the
timer status register with the OCF set, and then accessing the low byte (OCRL,
$0017) of the output compare registers. Resets have no effect on OCF.
TOF - TIMER OVERFLOW FLAG
The TOF bit is automatically set when the 16-bit timer counter rolls over from
$FFFF to $0000. Clear the TOF bit by reading the timer status register with the
TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.
Resets have no effect on TOF.
BIT 7
ICF
BIT 6
OCF
BIT 5
TOF
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
TSR
$0013
R
W
reset:
U
U
U
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 9-12. Timer Status Registers (TSR)
F
Freescale Semiconductor, Inc.
n
.
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