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參數(shù)資料
| 型號(hào)： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁(yè)數(shù)： | 33/98頁(yè) |
| 文件大?。?/td> | 1004K |
| 代理商： | HC05PL4GRS |
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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
RESETS
MOTOROLA
5-1
SECTION 5
RESETS
This section describes the four reset sources and how they initialize the MCU. A
reset immediately stops the operation of the instruction being executed, initializes
certain control bits, and loads the program counter with a user defined reset vec-
tor address. The following conditions produce a reset:
Initial power-up of device (power-on reset)
A logic zero applied to the RESET pin (external reset)
Time-out of the COP watchdog (COP reset)
Fetch of an opcode from an address not in the memory map
(illegal address reset)
Figure 5-1. Reset Sources
5.1
POWER-ON RESET
A positive transition on the V
DD
pin generates a power on reset. The power-on
reset is strictly for conditions during powering up and cannot be used to detect
drops in power supply voltage.
RESET
RESET
LATCH
R
C
COP WATCHDOG
POWER-ON RESET
ILLEGAL ADDRESS RESET
INTERNAL
ADDRESS BUS
D
INTERNAL
CLOCK
S
RST
TO CPU
AND
SUBSYSTEMS
V
DD
4-CYCLE
COUNTER
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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