參數(shù)資料
型號: HC05PL4GRS
英文描述: 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification
中文描述: 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范
文件頁數(shù): 55/98頁
文件大?。?/td> 1004K
代理商: HC05PL4GRS
April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
16-BIT PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
9-5
NOTE
To prevent interrupts from occurring between readings of the ACRH and ACRL,
set the I bit in the condition code register (CCR) before reading ACRH and clear
the I bit after reading ACRL.
9.3
INPUT CAPTURE REGISTERS
The input capture function is a technique whereby an external signal (connected
to PA2/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi-
ble to relate the timing of an external signal to the internal counter value, and
hence to elapsed time.
When the input capture circuitry detects an active edge on the selected source, it
latches the contents of the free-running timer counter registers into the input cap-
ture registers as shown in
Figure 9-6
.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter val-
ues at successive edges of opposite polarity measures the pulse width of the sig-
nal.
Figure 9-6. Timer Input Capture Block Diagram
The input capture registers are made up of two 8-bit read-only registers (ICRH,
ICRL) as shown in
Figure 9-7
. The input capture edge detector contains a Schmitt
trigger to improve noise immunity. The edge that triggers the counter transfer is
defined by the input edge bit (IEDG) in the TCR. Reset does not affect the con-
tents of the input capture registers.
I
ICRH ($0014)
16-BIT COUNTER
÷
4
INTERNAL
CLOCK
(XTAL
÷
2)
TIMER
INTERRUPT
TIMER CONTROL REG.
$0012
REQUEST
INPUT CAPTURE (ICF)
RESET
ICRL ($0015)
I
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
(
READ
ICRH
READ
ICRL
LATCH
I
EDGE
SELECT
& DETECT
LOGIC
I
TCAP
INTERNAL
DATA
BUS
F
Freescale Semiconductor, Inc.
n
.
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