參數(shù)資料
型號: HC05PL4GRS
英文描述: 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification
中文描述: 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范
文件頁數(shù): 49/98頁
文件大小: 1004K
代理商: HC05PL4GRS
April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
SYSTEM CLOCKS
MOTOROLA
8-1
SECTION 8
SYSTEM CLOCKS
This section describes the system clock options for the MC68HC05PL4.
8.1
SYSTEM CLOCK SOURCE AND FREQUENCY OPTION
The operating bus frequency of the MCU is dependent on the clock source (OSC1
or internal RC) and the clock divider ratio. These are selected in the System Clock
Control Register (SYSCR).
BIT 7
BIT 6
BIT 5
BIT 4
SYSCR
R
SYSDIV1
SYSDIV2
CKSEL1
CKSEL2
$001D
W
POR
0
0
1
Figure 8-1. System Clock Control Register (SYSCR)
SYSDIV1,SYSDIV2 — System Clock Divider Select
The SYSDIV1 and SYSDIV2 bits select the divide ratio for the clock source.
After power-on-reset, the default setting is divide by 2.
Table 8-1
shows the
divide ratios.
CKSEL1,CKSEL2 — System Clock Source Select
The CKSEL1 and CKSEL2 bits select the system clock source for the MCU. After
power-on-reset, the default setting is internal RC.
Table 8-2
shows the system
clock source options.
BIT 3
BIT 2
OSCF
BIT 1
RCF
BIT 0
FMODE
CKOSC
0
1
0
1
0
Table 8-1. System Clock Divider Select
SYSDIV1
SYSDIV2
DIV
0
0
2
0
1
4
1
0
8
1
1
16
Table 8-2. System Clock Source Select
CKSEL1
CKSEL2
Select Option
0
0
External from OSC1
0
1
External from OSC1
1
0
Internal RC
1
1
External from OSC1 (with RC enabled)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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