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| 型號(hào)： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁(yè)數(shù)： | 25/98頁(yè) |
| 文件大?。?/td> | 1004K |
| 代理商： | HC05PL4GRS |
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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
INTERRUPTS
MOTOROLA
4-1
SECTION 4
INTERRUPTS
The CPU can be interrupted by five different sources – one software and four
hardware:
Non-maskable Software Interrupt Instruction (SWI)
External Asynchronous Interrupt (IRQ)
16-Bit Timer
8-Bit Timer
Keyboard Interrupt
4.1
INTERRUPT VECTORS
Table 4-1
summarizes the reset and interrupt sources and vector assignments
Table 4-1. Vector Address for Interrupts and Reset
Function
Source
Local
Mask
None
None
COPON
1
Global
Mask
Priority
(1=Highest)
Vector
Address
Reset
Power-On Logic
RESET Pin
COP Watchdog
None
1
$1FFE-$1FFF
SWI
User Code
None
None
Same Priority
As Instruction
2
$1FFC-$1FFD
External IRQ
IRQ Pin
ICF Bit
TCF Bit
OCF Bit
T8IF Bit
KIF3 Bit
KIF2 Bit
KIF1 Bit
KIF0 Bit
—
—
IRQEN
ICIE
TCIE
OCIE
T8IE
KIE3
KIE2
KIE1
KIE0
—
—
I Bit
$1FFA-$1FFB
16-Bit Timer
I Bit
3
$1FF8-$1FF9
8-Bit Timer
I Bit
4
$1FF6-$1FF7
Keyboard
I Bit
5
$1FF4-$1FF5
Reserved
Reserved
—
—
—
—
$1FF2-$1FF3
$1FF0-$1FF1
NOTES:
1. COPON enables/disables the COP watchdog timer.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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