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| 型號： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁數(shù)： | 21/98頁 |
| 文件大?。?/td> | 1004K |
| 代理商： | HC05PL4GRS |
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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
CENTRAL PROCESSING UNIT
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
3-1
SECTION 3
CENTRAL PROCESSING UNIT
The MC68HC05PL4 has an 8k-bytes memory map. The stack has only 64 bytes.
Therefore, the stack pointer has been reduced to only 6 bits and will only
decrement down to $00C0 and then wrap-around to $00FF. All other instructions
and registers behave as described in this chapter.
3.1
REGISTERS
The MCU contains five registers which are hard-wired within the CPU and are not
part of the memory map. These five registers are shown in
Figure 3-1
and are
described in the following paragraphs.
Figure 3-1. MC68HC05 Programming Model
CONDITION CODE REGISTER
I
ACCUMULATOR
6
0
A
INDEX REGISTER
7
1
X
4
5
2
3
STACK POINTER
SP
14
8
15
9
12
13
10
11
PC
CC
1
1
1
1
1
0
0
0
0
0
0
0
0
PROGRAM COUNTER
H
N
Z
C
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
F
Freescale Semiconductor, Inc.
n
.
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