參數(shù)資料
型號： HC05PL4GRS
英文描述： 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification
中文描述： 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范
文件頁數(shù)： 67/98頁
文件大小： 1004K
代理商： HC05PL4GRS
April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
DIGITAL TO ANALOG CONVERTER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
11-1
SECTION 11
DIGITAL TO ANALOG CONVERTER
This section describes Digital-to-Analog module used for DTMF generation.
11.1
DAC CONTROL AND DATA REGISTER
DACEN - DAC Channel Enable
Ths read/write bit enables/disables the DAC module for DTMF output.
1 =
Enable DAC module and configure PA1/DTMF as DTMF output pin.
0 =
Disable DAC module and configure PA1/DTMF as general purpose
PA1 pin.
DA5-DA0
These bits determine the output voltage of the DAC channel. The output volt-
age value is determined by:
V
OUT
= (V
DD
x DA[0:5]) x 2
6
There are 64 evenly spaced voltage levels available between V
DD
and V
SS
. The
lowest voltage is V
SS
and the highest voltage is 63/64V
DD
.
11.2
DAC OPERATION DURING WAIT MODE
In WAIT mode, the DAC continues to output a fixed voltage level which is set by
the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if fur-
ther power saving is required in WAIT mode.
11.3
DAC OPERATION DURING STOP MODE
In STOP mode, the DAC continues to output a fixed voltage level which is set by
the DA5-DA0 bits. The DAC should be disabled by clearing the DACEN bit if fur-
ther power saving is required in STOP mode.
BIT 7
BIT 6
0
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DACDR
$000F
R
W
DACEN
DA5
DA4
DA3
DA2
DA1
DA0
reset:
0
0
0
0
0
0
0
0
Figure 11-1. DAC Control and Data Register
F
Freescale Semiconductor, Inc.
n
.
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