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| 型號： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁數(shù)： | 38/98頁 |
| 文件大?。?/td> | 1004K |
| 代理商： | HC05PL4GRS |
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GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
5-6
RESETS
MC68HC05PL4
REV 2.0
Does not affect the input capture edge bit (IEDG) in the TCR.
Does not affect the interrupt flags in the timer status register (TSR).
Does not affect the input capture registers (ICRH, ICRL).
Does not affect the output compare registers (OCRH, OCRL).
Therefore configure the port A pins PA2,PA3 as general I/O function. However the
timer is free running for interrupt process.
5.4.5 Keyboard Interrupt Interface
A reset has the following effects on the Keyboard Interrupt interface:
Clears all bits in Keyboard interrupt enable register (KIER) and
Keyboard interrupt disable
Clears all bits in Keyboard interrupt flag register (KIFR)
Clears all bits in Pull-Up enable register (PUER)
Therefore disables the Keyboard interrupt and leaves the shared port B pins as
general I/O. Any pending interrupt flag is cleared and the Keyboard interrupt is dis-
abled.
5.4.6 6-bit DAC Subsystem
A reset has the following effects on the DAC subsystem:
Clears all bits in DAC control Register, hence DAC subsystem is
disabled.
Therefore configure the port A pin PA1 as general I/O function.
5.4.7 System Clock Option Subsystem
At reset has the following effects on OSC clock subsystem
The internal RC is enabled and oscillating at around 500kHz
Internal clock divider selected to divide by 2 for bus frequency
5.4.8 Miscellaneous Subsystem
A P reset has the following effects on IRQ subsystem
IRQ is disabled and reset the IRQ selection as negative edge-triggered
and low level-triggered, hence the LED/IRQ pin function as LED output
pin
Therefore also disable the LED driver output, hence the LED/IRQ pin is in high
impedance state.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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