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| 型號： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁數(shù)： | 5/98頁 |
| 文件大小： | 1004K |
| 代理商： | HC05PL4GRS |
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April 30, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05PL4
REV 2.0
MOTOROLA
iii
TABLE OF CONTENTS
Section
Page
7.4
7.5
PORT C ...........................................................................................................7-3
SUMMARY OF PORT A AND PORT B SHARED PINS..................................7-3
SECTION 8
SYSTEM CLOCKS
SYSTEM CLOCK SOURCE AND FREQUENCY OPTION..............................8-1
SECTION 9
16-BIT PROGRAMMABLE TIMER
TIMER REGISTERS (TMRH, TMRL)...............................................................9-2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL)..................................9-4
INPUT CAPTURE REGISTERS ......................................................................9-5
OUTPUT COMPARE REGISTERS .................................................................9-6
TIMER CONTROL REGISTER (TCR).............................................................9-8
Miscellaneous Control and Status Register for Timer16 .............................9-9
TIMER STATUS REGISTER (TSR)...............................................................9-10
16-BIT TIMER OPERATION DURING WAIT MODE.....................................9-11
16-BIT TIMER OPERATION DURING STOP MODE....................................9-11
SECTION 10
8-BIT TIMER
OVERVIEW....................................................................................................10-1
TIMER8 CONTROL AND STATUS REGISTER (T8CSR).............................10-2
TIMER8 COUNTER REGISTER (T8CNTR)..................................................10-3
COMPUTER OPERATING PROPERLY (COP) WATCHDOG......................10-3
8-BIT TIMER OPERATION DURING WAIT MODE.......................................10-4
8-BIT TIMER OPERATION DURING STOP MODE......................................10-4
SECTION 11
DIGITAL TO ANALOG CONVERTER
DAC CONTROL AND DATA REGISTER ......................................................11-1
DAC OPERATION DURING WAIT MODE ....................................................11-1
DAC OPERATION DURING STOP MODE....................................................11-1
DAC CHARACTERISTICS ............................................................................11-2
SECTION 12
INSTRUCTION SET
ADDRESSING MODES.................................................................................12-1
Inherent......................................................................................................12-1
Immediate..................................................................................................12-1
Direct .........................................................................................................12-2
Extended....................................................................................................12-2
Indexed, No Offset.....................................................................................12-2
Indexed, 8-Bit Offset..................................................................................12-2
8.1
9.1
9.2
9.3
9.4
9.5
9.5.1
9.6
9.7
9.8
10.1
10.2
10.3
10.4
10.5
10.6
11.1
11.2
11.3
11.4
12.1
12.1.1
12.1.2
12.1.3
12.1.4
12.1.5
12.1.6
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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