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| 型號： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁數(shù)： | 52/98頁 |
| 文件大小： | 1004K |
| 代理商： | HC05PL4GRS |
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GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
9-2
16-BIT PROGRAMMABLE TIMER
For More Information On This Product,
Go to: www.freescale.com
MC68HC05PL4
REV 2.0
The basis of the capture/compare Timer is a 16-bit free-running counter which
increases in count with each internal bus clock cycle. The counter is the timing ref-
erence for the input capture and output compare functions. The input capture and
output compare functions provide a means to latch the times at which external
events occur, to measure input waveforms, and to generate output waveforms and
timing delays. Software can read the value in the 16-bit free-running counter at
any time without affect the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input capture and
output compare functions are pairs of 8-bit registers. Each register pair contains
the high and low byte of that function. Generally, accessing the low byte of a spe-
cific timer function allows full control of that function; however, an access of the
high byte inhibits that specific timer function until the low byte is also accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-four pres-
caler, the counter rolls over every 262,144 internal clock cycles. Timer resolution
with a 4 MHz crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare state are
controlled by the timer control register (TCR) located at $0012 and the status of
the interrupt flags can be read from the timer status register (TSR) located at
$0013.
9.1
TIMER REGISTERS (TMRH, TMRL)
The functional block diagram of the 16-bit free-running timer counter and timer
registers is shown in
Figure 9-2
. The timer registers include a transparent buffer
latch on the LSB of the 16-bit timer counter.
Figure 9-2. Timer Counter and Register Block Diagram
T
TMRH ($0018)
TMR LSB
16-BIT COUNTER
÷
4
INTERNAL
CLOCK
(XTAL
÷
2)
TIMER CONTROL REG.
$0012
TIMER
INTERRUPT
REQUEST
OVERFLOW (TOF)
RESET
TMRL ($0019)
T
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
($FFFC)
READ
TMRH
READ
TMRL
READ
LATCH
F
Freescale Semiconductor, Inc.
n
.
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