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參數(shù)資料
| 型號： | FMMT560A |
| 文件頁數(shù)： | 7/247頁 |
| 文件大?。?/td> | 2493K |
| 代理商： | FMMT560A |
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5
www.fairchildsemi.com
FM24C256 rev. A.2
F
BACKGROUND INFORMATION (I
2
C Bus)
As mentioned, the I
2
C bus allows synchronous bidirectional com-
munication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with a
valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condition.
In addition, since the I
2
C bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
control byte, must follow the START condition. For EEPROMs, the
first 4-bit of the control byte is 1010 binary for READ and WRITE
operations. This is then followed by the device selection bits A2, A1
and A0, and acts as the three most significant bits of the word
address.The final bit in the control byte determines the type of
operation performed (READ/WRITE). A "1" signifies a READ while
a "0" signifies a WRITE. The control byte is then followed by two bytes
that define the word address, which is then followed by the data byte.
The EEPROMs on the I
2
C bus may be configured in any manner
required, providing the total memory addressed does not exceed
512K bits (64K bytes). EEPROM memory addressing is controlled
by hardware configuring the A2, A1, and A0 pins (Device Address
pins) with pull-up or pull-down resistors. ALL UNUSED PINS
MUST BE GROUNDED (tied to V
SS
).
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD-
DRESS]-[BYTE ADDRESS]
Pin Description
SERIAL CLOCK (SCL)
Definitions
Word
8 bits (byte) of data
Page
64 sequential addresses (one byte each) that
may be programmed during a "Page Write"
programming cycle.
Master
Any I
2
C device CONTROLLING the transfer of
data (such as a microcontroller).
Slave
Device being controlled (EEPROMS are
always considered Slaves).
Transmitter
Device currently SENDING data on the bus
(may be either a Master or Slave).
Receiver
Device currently receiving data on the bus
(Master or Slave).
The SCL input is used to clock all data into and out of the device.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data to and from the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.
Device Address Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to V
or V
to configure the EEPROM address for multiple device configura-
tion. A total of eight different devices can be attached to the same
SDA bus.
Write Protection (WP
)
If WP is tied to V
, program WRITE operations onto the entire
array of the memory will not be executed. READ operations are
always available.
If WP is tied to V
, normal memory operation is enabled for
READ/WRITE over the entire 256K bit memory array.
This feature allows the user to assign the entire array of the memory
as ROM, which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.
Device Operation
The FM24C256xxx supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving devices as the receiver. The device
controlling the transfer is the master and the device that is con-
trolled is the slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations. There-
fore, the FM24C256xxx is considered a slave in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and are reserved for
indication of start and stop conditions. Refer to Figures 1 and 2.
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
FM24C256xxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command until this
condition has been met.
STOP CONDITION
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM24C256xxx to place the device in
the standby power mode.
SCL
SDA
IN
SDA
OUT
tF
tLOW
tHIGH
tR
tLOW
tAA
tDH
tBUF
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
DS800023-3
Bus Timing
Note 3:
SCL = Serial Clock Data
SDA = Serial Data I/O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| FMMT560TA | 功能描述:兩極晶體管 - BJT PNP High V 500V RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產(chǎn)品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2 |
| FMMT560TC | 功能描述:兩極晶體管 - BJT PNP HighV 500V RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產(chǎn)品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2 |
| FMMT576 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| FMMT589 | 制造商:Diodes Incorporated 功能描述:TRANSISTOR PNP SOT-23 |
| FMMT589 | 制造商:Diodes Incorporated 功能描述:TRANSISTOR PNP SOT-23 |
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