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參數(shù)資料
| 型號： | FMMT560A |
| 文件頁數(shù)： | 18/247頁 |
| 文件大小： | 2493K |
| 代理商： | FMMT560A |
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5
www.fairchildsemi.com
FM93C06
F
Functional Description
The FM93C06 device has 7 instructions as described below. Note
that the MSB of any instruction is a “1” and is viewed as a start bit
in the interface sequence. The next 8 bits carry the op code and
the 6-bit address for register selection.
Read (READ):
The READ instruction outputs serial data on the D0 pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a 16-bit serial-out shift register. A dummy bit (logical
0) precedes the 16-bit data output string. Output data changes are
initiated by a low to high transition of the SK clock.
Write Enable (WEN):
When V
is applied to the part, it 'powers-up' in the Write Disable
(WDS) state. Therefore, all programming modes must be pre-
ceded by a Write Enable (WEN) instruction. Once a Write Enable
instruction is executed, programming remains enabled until aWrite
Disable (WDS) instruction is executed or V
CC
is removed from the
part.
Erase (ERASE):
The ERASE instruction will program all bits in the specified
register to the logical “1” state. CS is brought low following the
loading of the last address bit. This falling edge of the CS pin
initiates the self-timed programming cycle.
The DO pin indicates the READY/BUSY status of the chip if CS is
brought high after a minimum time of t
. DO = logical “0” indicates
that the register, at the address specified in the instruction, has
been erased, and the part is ready for another instruction.
Write (WRITE):
The WRITE instruction is followed by the address and 16 bits of data
to be written into the specified address. After the last bit of data is
put in the data-in (DI) pin, CS must be brought low before the next
rising edge of the SK clock. This falling edge of the CS initiates the
self-timed programming cycle. The D0 pin indicates the READY/
BUSY status of the chip if CS is brought high after a minimum of t
CS
.
D0 = logical 1 indicates that the register at the address specified in
the instruction has been written with the data pattern specified in the
instruction and the part is ready for another instruction.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in
the memory array and set each bit to the logical “1” state. The Erase
All cycle is identical to the ERASE cycle except for the different op-
code. As in the ERASE mode, the DO pin indicates the READY/
BUSY status of the chip if CS is brought high after the t
CS
interval.
Write All (WRALL):
The WRALL instruction will simultaneously program all registers
with the data pattern specified in the instruction. As in the WRITE
mode, the DO pin indicates the READY/BUSY status of the chip
if CS is brought high after the t
CS
interval.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruction
disables all programming modes and should follow all program-
ming operations. Execution of a READ instruction is independent
of both the WEN and WDS instructions.
Note:
The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"
operation prior to the "WRITE" and "WRITE ALL" instructions. The "ERASE" and "ERASE
ALL" instructions are included to maintain compatibility with earlier technology EEPROMs.
Instruction Set for the FM93C06
Instruction
READ
WEN
ERASE
WRITE
ERAL
WRALL
WDS
SB
1
1
1
1
1
1
1
Op. Code
10
00
11
01
00
00
00
Address
00 A3 A2 A1 A0
11xxxx
00 A3 A2 A1 A0
00 A3 A2 A1 A0
10xxxx
01xxxx
00xxxx
Data
Comments
Reads data stored in memory, at specified address.
Write enable must precede all programming modes.
Erase selected register.
Writes selected register.
Erases all registers.
Writes all registers.
Disables all programming instructions.
D15-D0
D15-D0
Note:
Address bits A5 and A4 should be set to '0' for READ, ERASE and WRITE instructions.
x = Don't care
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