- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄370212 > FMMT560A PDF資料下載
參數(shù)資料
| 型號(hào)： | FMMT560A |
| 文件頁(yè)數(shù)： | 118/247頁(yè) |
| 文件大?。?/td> | 2493K |
| 代理商： | FMMT560A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)當(dāng)前第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)
6
www.fairchildsemi.com
FM93CS46 Rev. A
F
w
Functional Description
A typical Microwire cycle starts by first selecting the device
(bringing the CS signal high). Once the device is selected, a valid
Start bit (
“
1
”
) should be issued to properly recognize the cycle.
Following this, the 2-bit opcode of appropriate instruction should
be issued. After the opcode bits, the 6-bit address information
should be issued. For certain instructions, some (or all) of these
6 bits are don
’
t care values (can be
“
0
”
or
“
1
”
), but they should still
be issued. Following the address information, depending on the
instruction (WRITE and WRALL), 16-Bit data is issued. Other-
wise, depending on the instruction (READ and PRREAD), the
device starts to drive the output data on the DO line. Other
instructions perform certain control functions and do not deal with
data bits. The Microwire cycle ends when the CS signal is brought
low. However during certain instructions, falling edge of the CS
signal initiates an internal cycle (Programming), and the device
remains busy till the completion of the internal cycle. Each of the
10 instructions is explained in detail in the following sections.
Memory Instructions
Following five instructions, READ, WEN, WRITE, WRALL and
WDS are specific to operations intended for memory array. The
PRE pin should be held low during these instructions.
1) Read and Sequential Read (READ)
READ instruction allows data to be read from a selected location
in the memory array. Input information (Start bit, Opcode and
Address) for this instruction should be issued as listed under
Table1. Upon receiving a valid input information, decoding of the
opcode and the address is made, followed by data transfer from
the selected memory location into a 16-bit serial-out shift register.
This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)
is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit
(logical 0) precedes this 16-bit data output string. Output data
changes are initiated on the rising edge of the SK clock. After
reading the 16-bit data, the CS signal can be brought low to end
the Read cycle. The PRE pin should be held low during this cycle.
Refer Read cycle diagram.
This device also offers
“
sequential memory read
”
operation to
allow reading of data from the additional memory locations instead
of just one location. It is started in the same manner as normal read
but the cycle is continued to read further data (instead of terminat-
ing after reading the first 16-bit data). After providing 16-bit data,
the device automatically increments the address pointer to the
next location and continues to provide the data from that location.
Any number of locations can be read out in this manner, however,
after reading out from the last location, the address pointer points
back to the first location. If the cycle is continued further, data will
be read from this first location onward. In this mode of read, the
dummy-bit is present only when the very first data is read (like
normal read cycle) and is not present on subsequent data reads.
The PRE pin should be held low during this cycle. Refer Sequen-
tial Read cycle diagram.
2) Write Enable (WEN)
When V
is applied to the part, it
“
powers up
”
in the Write Disable
(WDS) state. Therefore, all programming operations (for both
memory array and Protect Register) must be preceded by a Write
Enable (WEN) instruction. Once a Write Enable instruction is
executed, programming remains enabled until a Write Disable
(WDS) instruction is executed or V
CC
is completely removed from
the part. Input information (Start bit, Opcode and Address) for this
WEN instruction should be issued as listed under Table1. The
device becomes write-enabled at the end of this cycle when the
CS signal is brought low. The PRE pin should be held low during
this cycle. Execution of a READ instruction is independent of WEN
instruction. Refer Write Enable cycle diagram.
3) Write (WRITE)
WRITE instruction allows write operation to a specified location in
the memory with a specified data. This instruction is valid only
when the following are true:
I
Device is write-enabled (Refer WEN instruction)
I
Address of the write location is not write-protected
I
PE pin is held high during this cycle
I
PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRITE instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes t
WP
time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
The status of the internal programming cycle can be polled at any
time by bringing the CS signal high again, after t
CS
interval. When
CS signal is high, the DO pin indicates the READY/BUSY status
of the chip. DO = logical 0 indicates that the programming is still
in progress. DO = logical 1 indicates that the programming is
finished and the device is ready for another instruction. It is not
required to provide the SK clock during this status polling. While
the device is busy, it is recommended that no new instruction be
issued. Refer Write cycle diagram.
It is also recommended to follow this instruction (after the device
becomes READY) with a Write Disable (WDS) instruction to
safeguard data against corruption due to spurious noise, inadvert-
ent writes etc.
4) Write All (WRALL)
Write all (WRALL) instruction is similar to the Write instruction
except that WRALL instruction will simultaneously program all
memory locations with the data pattern specified in the instruction.
This instruction is valid only when the following are true:
I
Protect Register has been cleared (Refer PRCLEAR
instruction)
I
Device is write-enabled (Refer WEN instruction)
I
PE pin is held high during this cycle
I
PRE pin should be held low during this cycle
Input information (Start bit, Opcode, Address and Data) for this
WRALL instruction should be issued as listed under Table1. After
inputting the last bit of data (D0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes t
time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Write All
cycle diagram.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FMMT92CSM | General Purpose PNP Transistor In a Hermetically Sealed Ceramic Surface Mount Package(通用PNP晶體管( 陶瓷表貼封裝)) |
| FMMT92CSM | GENERAL PURPOSE PNP TRANSISTOR IN A HERMETICALLY SEALED CERAMIC SURFACE MOUNT PACKAGE |
| FMN1.1 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | CHIP |
| FMN1.2 | TRANSISTOR | MOSFET | N-CHANNEL | 33V V(BR)DSS | CHIP |
| FMN35.3 | TRANSISTOR | MOSFET | N-CHANNEL | 33V V(BR)DSS | CHIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FMMT560TA | 功能描述:兩極晶體管 - BJT PNP High V 500V RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產(chǎn)品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2 |
| FMMT560TC | 功能描述:兩極晶體管 - BJT PNP HighV 500V RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產(chǎn)品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2 |
| FMMT576 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述: |
| FMMT589 | 制造商:Diodes Incorporated 功能描述:TRANSISTOR PNP SOT-23 |
| FMMT589 | 制造商:Diodes Incorporated 功能描述:TRANSISTOR PNP SOT-23 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。