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| 型號(hào)： | FMMT560A |
| 文件頁(yè)數(shù)： | 235/247頁(yè) |
| 文件大小： | 2493K |
| 代理商： | FMMT560A |
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PRODUCT SPECIFICATION
FMS2701
12
P
There are five steps within an SMBus cycle:
1.
Start signal
2.
Slave address byte
3.
Pointer register address byte
4.
Data byte to read or write
5.
Stop signal
When the SMBus interface is inactive (SCL = H and SDA = H)
communications are initiated by sending a start signal. The
start signal (Figure 5, left waveform) is a HIGH-to-LOW
transition on SDA while SCL is HIGH. This signal alerts all
slaved devices that a data transfer sequence is imminent.
After a start signal, the first eight bits of data that are transferred,
comprise a seven bit slave address followed a single R/W bit
(Read = H, Write = L). As shown in Figure 6, the R/W bit
indicates the direction of data transfer: read from; or write to
the slave device. If the transmitted slave address matches the
address of the FMS2701 which set by the state of the ADD
pin, the FMS2701 acknowledges by pulling SDA LOW on
the 9th SCL pulse (see Figure 7) to send an acknowledge bit,
ACK. If the addresses do not match, the FMS2701 does not
acknowledge.
For each byte of data read or written, the MSB is the first bit
of the sequence.
DATA TRANSFER
If a slave device such as the FMS2701 does not acknowledge
the master device during a write sequence, SDA remains HIGH
so that the master can generate a stop signal. During a read
sequence, if the master device does not acknowledge (ACK = L),
the FMS2701 interprets this as “end of data.” SDA remains
HIGH so the master can generate a stop signal.
To write data to a specific FMS2701 control register, three
bytes are sent:
1.
Write the slave address byte with bit R/W = L.
2.
Write the pointer byte.
3.
Write to the control register indexed by the pointer.
Data is read from the control registers of the FMS2701 in a
similar manner, except that two data transfer operations are
required:
1.
Write the slave address byte with bit R/W = L.
2.
Write the pointer byte.
3.
Write the slave address byte with bit R/W = H
4.
Read the control register indexed by the pointer.
Preceding each slave write, there must be a start cycle. Follow-
ing the pointer byte there should be a stop cycle. After the last
read, there must be a stop cycle comprising a LOW-to-HIGH
transition of SDA while SCL is HIGH. (see Figure 5, right
waveform)
A repeated start signal occurs when the master device driv-
ing the serial interface generates a start signal without first
generating a stop signal to terminate the current communica-
tion. This is used to change the mode of communication
(read, write) between the slave and master without releasing
the serial interface lines.
Serial Interface Read/Write Examples
Examples below show how serial bus cycles can be linked
together for multiple register read and write access cycles.
For sequential register accesses, each ACK handshake ini-
tiates further SCL clock cycles from the master to transfer
the next data byte.
Write to one control register
1.
Start signal
2.
Slave Address byte (R/W bit = LOW)
3.
Pointer byte
4.
Data byte to base address
5.
Stop signal
Read from one control register
1.
Start signal
2.
Slave Address byte (R/W bit = LOW)
3.
Pointer byte (= base address)
4.
Stop signal
5.
Start signal
6.
Slave Address byte (R/W bit = HIGH)
7.
Data byte from base address
8.
Stop signal
Addressable Memory
Although the FMS2701 will respond to external inputs, con-
trol of the operation of the FMS2701 is through the internal
registers. Following power-up, registers are set to default
values. After a 140 msec. power up reset delay, the FMS2701
will begin checking sensor inputs to determine if the temper-
ature in voltages fall within default limits.
These default values may be overridden by changing the val-
ues stored in the Value RAM. If the PTA
7-0
and PTR
7-0
val-
ues are changed, then the TRIP_LOCK (Temperature Trip
Point Lock) bit in the Configuration Register must be set to
enable temperature values to be compared against the pro-
grammable rather than the fixed trip point values. If the tem-
perature limit values are changed, then the changes are
effective immediately. Interrupt masking (register 0x43),
enabling (INT_EN bit) and clearing (INT_CLR bit) can be
used to disable interrupts during register setup.
There are four control registers and 21 Value RAM locations,
with functions and bit assignments defined in the Address-
able Memory section.
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