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FM93C56
F
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltage
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
ESD Rating
DC and AC Electrical Characteristics
V
CC
= 2.7V to 5.5V unless otherwise specified
–65
°
C to +150
°
C
+6.5V to -0.3V
+300
°
C
2000V
Symbol
Parameter
Part Number
Conditions
Min.
Max.
Units
I
CCA
I
CCS
Operating Current
Standby Current
L
LZ
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
CS = V
IH
, SK = 250KHz
CS = V
IL
1
mA
10
1
±
1
μ
A
μ
A
μ
A
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
SK
t
SKH
t
SKL
t
SKS
V
IN
= 0V to V
CC
(Note 2)
-0.1
0.8 V
CC
0.15 V
CC
V
CC
+1
0.1 V
CC
V
I
OL
= 10
μ
A
I
OH
= -10
μ
A
(Note 3)
V
V
0.9 V
CC
0
1
1
0.2
250
KHz
μ
s
μ
s
μ
s
SK must be at V
IL
for
t
before CS goes
high
(Note 4)
t
CS
Minimum CS
Low Time
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
1
μ
s
t
CSS
t
DH
t
DIS
t
CSH
t
DIH
t
PD
t
SV
t
DF
t
WP
0.2
70
0.4
0
0.4
μ
s
ns
μ
s
ns
μ
s
μ
s
μ
s
μ
s
ms
2
1
CS = V
IL
0.4
15
Operating Range
Ambient Operating Temperature
FM93C56L/LZ
FM93C56LE/LZE
FM93C56LV/LZV
Power Supply (V
CC
)
0
°
C to +70
°
C
-40
°
C to +85
°
C
-40
°
C to +125
°
C
2.7V to 5.5V
Capacitance
T
A
= 25
°
C, f = 1 MHz (Note 5)
Symbol
Test
Typ
Max
Units
C
OUT
C
IN
Output Capacitance
Input Capacitance
5
5
pF
pF
Note 1
:
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Stress above those listed under “Absolute Maximum Ratings” may cause permanent
Note 2
:
Typical leakage values are in the 20nA range.
Note 3
:
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both t
SKH
and t
limits must be observed.
Therefore, it is not allowable to set 1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 4
:
CS (Chip Select) must be brought low (to V
) for an interval of t
in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the
opcode diagram on the following page.)
The shortest allowable SK clock period = 1/f
(as shown under the f
parameter).
Note 5
:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
V
CC
Range
V
IL
/V
IH
Input Levels
.03V/1.8V
V
IL
/V
IH
V
OL
/V
OH
Timing Level
0.8V/1.5V
I
OL
/I
OH
Timing Level
1.0V
2.7V
≤
V
CC
≤
5.5V
(Extended Voltage Levels)
4.5V
≤
V
CC
≤
5.5V
(TTL Levels)
±
10
μ
A
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
2.1mA/-0.4mA
Output Load: 1 TTL Gate (C
L
= 100 pF)