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| 型號： | FBGA |
| 英文描述： | FBGA - FBGA User＇s Guide. Version 4.2 |
| 中文描述： | FBGA封裝- FBGA封裝用戶指南。版本4.2 |
| 文件頁數(shù)： | 76/97頁 |
| 文件大?。?/td> | 2624K |
| 代理商： | FBGA |
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FBGA User’s Guide
Version 4.2, November 1, 2002
75
Figure 1 shows the smaller size of CSPs
next to a comparable density TSOP.
Figure 2 shows a cross-section of the die-down configuration of a
μ
BGA package.
to the end-use printed circuit board
(PCB). While DCA technology of-
fers the ultimate in miniaturiza-
tion, the infrastructure for it is not
established enough for DCA to be
cost competitive. Moreover, DCA
is not a viable option when the die
has been designed for wirebonded
interconnects (i.e., the bond pads
are located around the periphery of
the die), as is the case with all flash
memories in traditional leaded
packages. DCA is better suited for
die having the bond pads in an
array across the die surface, en-
abling the connections to be made
with flip-chip technology instead
of conventional wirebonding.
Figure 1 shows the smaller foot-
print of a CSP next to a comparable
density TSOP. The smaller form/fit
factor saves considerable board
space and provides a lower profile
– all of which is needed when try-
ing to cram more memory capacity
onto ever smaller motherboards,
or in products striving to fit into
the palm of your hand.
NOT JUST ANY CSP WILL DO
In addressing the demand for a
flash memory CSP, AMD first
looked at the
μ
BGA, since market
acceptance of it was already es-
tablished. AMD’s LV800 flash
family was initially offered in a
μ
BGA, and we shipped modest
quantities of it. But these early
μ
BGA package designs included
polyimide tape embedded with
solid gold traces for routing the
signals from the die to the exter-
nal terminals, and this was too
costly. So we had the polyimide
tape replaced with a copper core
tape that had gold-plated copper
traces ("beam leads") instead of
solid gold. This flash gold was
bondable and kept oxidation from
growing, and the copper brought
the costs down. We ran into a
roadblock, however, when our
supplier was unable to produce
the copper core tape in sufficient
quantities. It was a roadblock that
soon proved to be a blessing in
disguise.
Faced with no reliable, cost-
effective CSP to offer flash cus-
tomers, we turned to Fijitsu,
AMD's FASL business partner.
Fijitsu had an FBGA with a
polyimide tape substrate that
looked promising, so we got per-
mission to adopt their package
technology. Besides being cheaper
than the
μ
BGA, the FBGA con-
struction was appealing because
the package size could remain the
same even if the die size became
smaller. To better understand this,
it helps to look at the configura-
tion of an FBGA versus a
μ
BGA.
μ
BGA CONSTRUCTION –
ONE DIE SIZE ONLY PLEASE
The
μ
BGA package is not like a
standard IC package in which you
attach a die. It is a construction
that is built on top of the die, so
the package is nearly the same
size as the die itself. The cross-
section drawing in Figure 2 shows
the die-down configuration, in-
terconnected by gold-plated beam
leads to traces that route through
the polyimide tape to an array of
external solder balls.
This package construction pre-
sented a problem for AMD be-
cause of our die size. For many of
the popular densities of the time,
our die size was smaller than any
other flash manufacturer’s. While
this is good for keeping fab costs
down (more die per wafer), our
die size was too small to provide
room for the size of the solder
ball array while keeping the pitch
(the distance between the
centerlines of adjacent solder
balls) at a manageable 0.75 mm
for board assembly. Moreover,
even if our die could have fit ini-
tially, every time we implemented
a die shrink we would face the
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