FBGA User’s Guide
Version 4.2, November 1, 2002
61
Chapter 9:
Board Level Characterization Studies
As part of an internal characterization study and ongoing product improvement program, AMD has
conducted board-level testing of the FBGA package for Flash memory.
The testing includes copper lead frame TSOP as a benchmark. As of late January 1999, the results are
as follows.
AMD intends to continue the testing until 63% failures occurs or until 9,000 cycles are completed,
whichever occurs sooner.
Experimental Design and Procedure
Board Design
CSP test boards were designed to have six packages (of one package type) on each board, to ensure
adequate spacing between adjacent packages. Space considerations limited the TSOP boards to four
TSOPs per board. On each board, half the packages were oriented at 90° to the other half. These
precautions ensure that the data collected is free of any effects of location / orientation.
All the packages have a daisy chained die in them. The daisy chain circuit is completed on the board
level so that each package consists of a single net. Any failure on any solder ball can be immediately
captured as a break in the daisy chain.
The board is 20 mils thick, which replicates the construction of a standard PCMCIA card.
Board Fabrication
Standard printed circuit board (PCB) processes were used in the fabrication of the boards.
16 Mb FBGA-BT (ASE)
16 Mb TSOP I 48-Pin
Test:
0/100°C
Test:
0/100°C
Cycles completed:
7847
Cycles completed:
7847
Sample size:
54
Sample size:
40
Failure #
Cycle #
Failure #
Cycle #
1st
5800
1st
5560
2nd
6521
2nd
5708
3rd
4th
6581
7312
3rd
5868
5th
7512
6th
7512
7th
7662