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PCI Bus Host Bridge Registers
6-10
élanSC520 Microcontroller Register Set Manual
Programming Notes
This register is reset by a system reset. The bits in this register are not affected by a PCI bus reset. A PCI bus reset
is initiated by setting the PCI_RST bit in the HBCTL register (see page 6-3).
Interrupt status bits are set whenever the associated event occurs regardless of the corresponding interrupt enable bit.
9
M_RPER_
IRQ_SEL
Master Received Parity Error Interrupt Select
This bit allows the assertion of the parity error signal (PERR) during a master controller write
transaction or during the address phase of a master controller read transaction to generate an
NMI instead of a maskable interrupt.
0 =Master write transactions or master read address phase cycles that detect the parity error
signal asserted generate a maskable interrupt.
1 =Master write transactions or master read address phase cycles that detect the parity error
signal asserted generate an NMI.
8
M_DPER_
IRQ_SEL
Master Detected Parity Error Interrupt Select
This bit allows parity errors detected by the master controller during a read transaction to
generate an NMI instead of a maskable interrupt.
0 =Master read transactions that detect a parity error generate a maskable interrupt.
1 =Master read transactions that detect a parity error generate an NMI.
7
–
6
Reserved
Reserved
This bit field should be written to 0 for normal system operation.
5
M_RTRTO_
IRQ_ENB
Master Retry Time-Out Interrupt Enable
This bit allows master retry time-outs to generate an interrupt.
0 =Master retry time-outs do not generate an interrupt.
1 =Master retry time-outs generate an interrupt.
4
M_TABRT_
IRQ_ENB
Master Target Abort Interrupt Enable
This bit allows master controller transactions that are terminated with a target abort to
generate an interrupt.
0 =Master transactions that are terminated with a target abort do not generate an interrupt.
1 =Master transactions that are terminated with a target abort generate an interrupt.
3
M_MABRT_
IRQ_ENB
Master Abort Interrupt Enable
This bit allows master controller transactions that are terminated with a master abort to
generate an interrupt.
0 =Master transactions that are terminated with a master abort do not generate an interrupt.
1 =Master transactions that are terminated with a master abort generate an interrupt.
2
M_SERR_
IRQ_ENB
Master System Error Interrupt Enable
This bit allows the assertion of the system error signal (SERR) by a PCI bus agent to generate
an interrupt.
0 =Assertion of the system error signal does not generate an interrupt.
1 =Assertion of the system error signal generates an interrupt.
1
M_RPER_
IRQ_ENB
Master Received Parity Error Interrupt Enable
This bit allows the assertion of the parity error signal (PERR) during a master controller write
transaction or during the address phase of a master controller read transaction to generate an
interrupt.
0 =Master write transactions or master read address phase cycles that detect the parity error
signal asserted do not generate an interrupt.
1 =Master write transactions or master read address phase cycles that detect the parity error
signal asserted generate an interrupt.
0
M_DPER_
IRQ_ENB
Master Detected Parity Error Interrupt Enable
This bit allows parity errors detected by the master controller during a read transaction to
generate an interrupt.
0 =Master read transactions that detect a parity error do not generate an interrupt.
1 =Master read transactions that detect a parity error generate an interrupt.
Bit
Name
Function