
General-Purpose Timer Registers
14-4
élanSC520 Microcontroller Register Set Manual
13
INT_ENB
GP Timer 0 Interrupt Enable
This bit allows the timer to generate an interrupt when the timer counter value reaches a
maximum count compare register value.
0 =GP Timer 0 interrupt request generation is disabled.
1 =GP Timer 0 interrupt request generation is enabled.
If the INT_ENB bit is 1, the T0_INT_STA bit is set in the GPTMRSTA register (see
page 14-2) and an interrupt is generated when one of the following conditions occurs:
The ALT_CMP bit is 1 (see page 14-5) and the GPTMR0CNT register value
(page 14-6) equals the value of either register GPTMR0MAXCMPA (page 14-7) or
GPTMR0MAXCMPB (page 14-8).
The ALT_CMP bit is 0 and the GPTMR0CNT register value equals the value of the
GPTMR0MAXCMPA register only.
When the INT_ENB bit is 0, the timer does not cause the T0_INT_STA bit to be set in
the GPTMRSTA register (see page 14-2), and therefore a timer interrupt is not
generated.
Before GP Timer 0 interrupts are enabled, the GPTMR0MAP register (see page 12-21)
must be configured to route the interrupt to the appropriate interrupt request level and
priority.
I
I
12
MAX_CNT_RIU
GP Timer 0 Maxcount Compare Register In Use
This bit can be used by software with the MAX_CNT bit to determine where the timer is
in its current count sequence.
0 =Hardware clears this MAX_CNT_RIU bit when the GPTMR0MAXCMPA register (see
page 14-7) is being used for comparison to the GP Timer 0 count value.
1 =Hardware sets this MAX_CNT_RIU bit when the GPTMR0MAXCMPB register (see
page 14-8) is being used for comparison to the GP Timer 0 count value.
Hardware also clears this bit any time hardware disables the timer by clearing the ENB
bit (i.e., at the end of the timer count when in noncontinuous mode). See the
CONT_CMP bit description on page 14-5.
11
–
6
Reserved
Reserved
This bit field should be written to 0 for normal system operation.
5
MAX_CNT
GP Timer 0 Maximum Count
This bit can be used by software with the MAX_CNT_RIU bit to determine where the
timer is in its current count sequence.
0 =Software must clear this bit by writing a 0 to it. This bit is never automatically cleared
by hardware.
1 =This bit is set by hardware any time the timer count value reaches a maximum count
value (maximum count value A or maximum count value B). This bit cannot be set by
software.
When GP Timer 0 is in alternate compare mode (the ALT_CMP bit = 1), the MAX_CNT
bit is set whenever the timer 0 count value equals the value of either register
GPTMR0MAXCMPA (see page 14-7) or GPTMR0MAXCMPB (page 14-8). The
MAX_CNT bit is set for this condition regardless of the state of the INT_ENB bit.
The MAX_CNT bit can be used to monitor timer status through software polling instead
of making use of interrupt generation.
4
RTG
GP Timer 0 Retrigger
This bit determines the control function provided by the GP Timer 0 input pin (TMRIN0)
when TMRIN0 is not configured as the timer clock source (i.e., when the EXT_CLK bit
is 0).
0 =A high level on the TMRIN0 input pin allows the timer to count and a Low level on
this pin holds the timer count value constant.
1 =If the timer is enabled, a 0 to 1 edge transition on the TMRIN0 pin resets the existing
GP Timer 0 count value and then counting continues.
This bit is ignored when external clocking is selected (i.e., when the EXT_CLK bit is 1).
Bit
Name
Function