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Index
Index-6
élanSC520 Microcontroller Register Set Manual
Drive Strength Control register, 20-10
DRQSEN bit field
in MSTDMACTL register, 11-87
in SLDMACTL register, 11-51
drqx internal signal, 11-51, 11-87
DS_ENB bit field, 17-17
DSCTL register, 20-10
DSR bit field, 18-23
DSR2 Function Select bit field, 20-5
DSRx signal
in UARTxMCR register, 18-19, 18-20
in UARTxMSR register, 18-23, 18-24
DTR bit field, 18-20
DTRx signal, 18-19, 18-20
E
ECC check bit and data bit positions (figure), 7-11
ECC Check Bit Position register, 7-11
ECC Check Code Test register, 7-12
ECC check codes and associated data (table), 7-13
ECC Control register, 7-9
ECC Data Bit Position bit field, 7-11
ECC Enable for All Four Banks bit field, 7-9
ECC Interrupt Mapping register, 12-19
ECC Multi-Bit Error Address bit field, 7-15
ECC Multi-Bit Error Address register, 7-15
ECC NMI Enable bit field, 12-19
ECC Single-bit Error Address bit field, 7-14
ECC Single-Bit Error Address register, 7-14
ECC Status register, 7-10
ECC_CHK_POS bit field, 7-11
ECC_ENB bit field, 7-9
ECC_IRQ_MAP bit field, 12-20
ECC_NMI_ENB bit field, 12-19
ECCCKBPOS register, 7-11
ECCCKTEST register, 7-12
ECCCTL register, 7-9
ECCMAP register, 12-19
ECCMBADD register, 7-15
ECCSBADD register, 7-14
ECCSTA register, 7-10
élanSC520 Microcontroller Revision ID register, 4-2
EMSI bit field, 18-11
Enable Bad ECC Check Bits bit field, 7-12
ENABLE bit field
in CBAR register, 2-9
in PCICFGADR register, 6-15
Enable bit field
in CBAR register, 2-9
in PCICFGADR register, 6-15
Enable Modem Status Interrupt bit field, 18-11
Enable Multi-Bit Interrupt bit field, 7-9
Enable Received Data Available Interrupt bit field, 18-11
Enable Receiver Line Status Interrupt bit field, 18-11
Enable Single-bit Interrupt bit field, 7-9
Enable Transmitter Holding Register Empty Interrupt bit
field, 18-11
Enable UART x Interrupts bit field, 18-19
ENB bit field
in GPTMR0CTL register, 14-3
in GPTMR1CTL register, 14-9
in GPTMR2CTL register, 14-15
in WDTMRCTL register, 16-2
End of Current Buffer in Channel x bit field, 11-22, 11-23
ENH_MODE_ENB bit field, 11-4
Enhanced Mode Enable bit field, 11-4
Enter AMDebug Technology Mode on Next Reset bit
field, 3-3
EOI bit in R_SL_EOI bit field, 12-28, 12-41, 12-53
EPS bit field, 18-17
ERDAI bit field, 18-11
ERLSI bit field, 18-11
ERR_IN_FIFO bit field, 18-21
ESMM_SMM bit field
in MPICOCW3 register, 12-30
in S1PICOCW3 register, 12-55
in S2PICOCW3 register, 12-43
ETHREI bit field, 18-11
Even Parity Select bit field, 18-17
EXP_SEL bit field, 16-3
Exponent Select bit field, 16-3
EXT_CLK bit field
in GPTMR0CTL register, 14-5
in GPTMR1CTL register, 14-11
F
Fast Back-to-Back Capable bit field, 6-20
FBTB bit field, 6-20
FE bit field, 18-22
ferr internal signal, 12-61
FERRMAP register, 12-21
FIFO Enable bit field
in UARTxFCR register, 18-16
in UARTxFCRSHAD register, 18-6
FIFO Mode Indication bit field, 18-12
in UARTxFCR register, 18-16
in UARTxFCRSHAD register, 18-6