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Index
Index-18
élanSC520 Microcontroller Register Set Manual
SDRAM Bank 0–3 Ending Address register, 7-7
SDRAM Bank Configuration register, 7-5
SDRAM Buffer Control register, 8-2
SDRAM CAS Latency bit field, 7-4
SDRAM Control register, 7-2
SDRAM controller MMCR registers (table), 7-1
SDRAM ECC Interrupt Mapping bit field, 12-20
SDRAM Operation Mode Select bit field, 7-3
SDRAM RAS Precharge Delay bit field, 7-4
SDRAM RAS-to-CAS Delay bit field, 7-4
SDRAM Refresh Request Speed bit field, 7-2
SDRAM Timing Control register, 7-4
SECOND bit field, 17-4
Select Counter x bit field, 13-11
Select ICW1 bit field
in MPICICW1 register, 12-26
in MPICOCW2 register, 12-28
SERR Enable bit field, 6-20
SERR signal
in HBMSTIRQCTL register, 6-9, 6-10
in PCISTACMD register, 6-13, 6-19, 6-20
SERR_ENB bit field, 6-20
SET bit field, 17-16
Set Break Enable bit field, 18-17
SFNM bit field
in MPICICW4 register, 12-35
in S1PICICW4 register, 12-59
in S2PICICW4 register, 12-47
SGL_INT_ENB bit field, 7-9
SIG_SERR bit field, 6-19
Signal Width
for (GPIOWR and GPMEMWR) bit field, 10-12
for GPALE bit field, 10-14
for GPIORD and GPMEMRD bit field, 10-10
for the GP Bus Chip Selects bit field, 10-8
Signaled System Error bit field, 6-19
Signaled Target Abort bit field, 6-20
Single PIC bit field
in MPICICW1 register, 12-26
in S1PICICW1 register, 12-52
in S2PICICW1 register, 12-40
Single-bit ECC Error bit field, 7-10
SL bit in R_SL_EOI bit field, 12-28, 12-41, 12-53
SL1PICMODE register, 12-8
SL2PICMODE register, 12-9
Slave 1 PIC
I/O Port 00A0h access summary (table), 12-52
Initialization Control Word 1 register, 12-51
Initialization Control Word 2 register, 12-57
Initialization Control Word 3 register, 12-58
Initialization Control Word 4 register, 12-59
In-Service register, 12-50
Interrupt Mask register, 12-60
Interrupt Mode register, 12-8
Interrupt Request register, 12-49
Operation Control Word 2 register, 12-53
Operation Control Word 3 register, 12-55
Slave 2 PIC
I/O Port 0024h access summary (table), 12-40
Initialization Control Word 1 register, 12-39
Initialization Control Word 2 register, 12-45
Initialization Control Word 3 register, 12-46
Initialization Control Word 4 register, 12-47
In-Service register, 12-38
Interrupt Mask register, 12-48
Interrupt Mode register, 12-9
Interrupt Request register, 12-37
Operation Control Word 2 register, 12-41
Operation Control Word 3 register, 12-43
Slave DMA.
See also
DMA, GP-DMA, Master DMA.
Slave DMA Channel 0
Memory Address register, 11-42
Page register, 11-69
Transfer Count register, 11-43
Slave DMA Channel 0–3
Control register, 11-51
Mask register, 11-54
Mode register, 11-55
Status register, 11-50
Slave DMA Channel 1
Memory Address register, 11-44
Page register, 11-65
Transfer Count register, 11-45
Slave DMA Channel 2
Memory Address register, 11-46
Page register, 11-63
Transfer Count register, 11-47
Slave DMA Channel 3
Memory Address register, 11-48
Page register, 11-64
Transfer Count register, 11-49
Slave DMA Clear Byte Pointer register, 11-57
Slave DMA Controller Reset register, 11-58
Slave DMA Controller Temporary register, 11-59
Slave DMA General Mask register, 11-61
Slave DMA Mask Reset register, 11-60
Slave Software DRQ(n) Request register, 11-53