參數(shù)資料
型號(hào): EDI416S4030A10SI
英文描述: 1Mx 16 Bits x 4 Banks Synchronous DRAM(100MHz,1M x 16 位 x 4 組同步動(dòng)態(tài)RAM)
中文描述: 1Mx 16位× 4個(gè)銀行同步DRAM(100MHz的,100萬(wàn)× 16位× 4個(gè)組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 8/26頁(yè)
文件大?。?/td> 353K
代理商: EDI416S4030A10SI
16
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
FIG. 7 PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH=4
RAS
CAS
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE
CAc
CBd
RBb
CAa
RAa
DQ
Write
(A-Bank)
Write
(B-Bank)
Row Active
(B-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RAa
DAa3
DBb0
DBb1
DBb2
DBb3
DAc0
DAc1
DBd0
DBd1
DAa1
DAa0
DAa2
DON'T CARE
CBb
Note 2
Note 1
RBb
tRDL
tCDL
NOTES:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
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