參數(shù)資料
型號(hào)： EDI416S4030A10SI
英文描述： 1Mx 16 Bits x 4 Banks Synchronous DRAM(100MHz,1M x 16 位 x 4 組同步動(dòng)態(tài)RAM)
中文描述： 1Mx 16位× 4個(gè)銀行同步DRAM（100MHz的，100萬(wàn)× 16位× 4個(gè)組同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 12/26頁(yè)
文件大?。?/td> 353K
代理商： EDI416S4030A10SI
2
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Signal
Polarity
Function
CLK
Input
Pulse
Positive Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
CKE
Input
Level
Active High
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock,
CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
CE
Input
Pulse
Active Low
CE disable or enable device operation by masking or enabling all inputs except CLK, CKE and DQM.
RAS, CAS
Input
Pulse
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
WE
executed by the SDRAM.
BA0,BA1
Input
Level
—
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the
rising clock edge.
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the
A0-11,
rising clock edge. In addition to the row address, A10/AP is used to invoke Autoprecharge operation at
A10/AP
Input
Level
—
the end of the Burst Read or Write cycle. If A10/AP is high, autoprecharge is selected and BA0, BA1
defines the bank to beprecharged . If A10/AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If A10/AP is high, all banks will be precharged regardless of the state of BA0,
BA1. If A10/AP is low, then BA0, BA1 is used to define which bank to precharge.
DQ0-15
Input/Output
Level
—
Data Input/Output are multiplexed on the same pins.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In
L(U)DQM
Input
Pulse
Mask
Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable.
Active High
In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be
written if it is lowbut blocks the Write operation if DQM is high.
VDD, VSS
Supply
Power and ground for the input buffers and the core logic.
VDDQ, VSSQ
Supply
Isolated power and ground for the output buffers to improve noise immunity.
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參數(shù)描述
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