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參數(shù)資料
| 型號： | EDI416S4030A10SI |
| 英文描述： | 1Mx 16 Bits x 4 Banks Synchronous DRAM(100MHz,1M x 16 位 x 4 組同步動態(tài)RAM) |
| 中文描述： | 1Mx 16位× 4個銀行同步DRAM（100MHz的，100萬× 16位× 4個組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 21/26頁 |
| 文件大?。?/td> | 353K |
| 代理商： | EDI416S4030A10SI |
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
REFRESH CYCLE PARAMETERS
-10
-12
Parameter
Symbol
Min
Max
Min
Max
Units
Notes
Refresh Period
tREF
—64—64
ms
1, 2
Self Refresh Exit Time
tSREX
tRFC
—tRFC
—ns
3
NOTES:
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.
3. The self refresh is exited by restarting the external clock and then asserting CKE high. This must be followed by NOPs for a minimum time of tRFC before the SDRAM
reaches idle state to begin normal operation.
Parameter
Symbol
-10
-12
Units
Notes
Min
Max
Min
Max
CAS latency = 3
10
1000
12
1000
CAS latency = 2
13
1000
15
1000
Clock to Valid Output Delay
tSAC
7
8
ns
1, 2
Output Data Hold Time
tOH
33
ns
2
Clock High Pulse Width
tCH
3.5
4.0
ns
3
Clock Low Pulse Width
tCL
3.5
4.0
ns
3
Input Setup Time
tSS
2.5
3
ns
3
Input Hold Time
tSH
11
ns
3
Clock to Output in Low-Z
tSLZ
11
ns
2
Clock to Output in High-Z
tSHZ
78
ns
Row Active to Row Active Delay
tRRD
20
24
ns
4
RAS to CAS Delay
tRCD
24
26
ns
4
Row Precharge Time
tRP
24
26
ns
4
Row Active Time
tRAS
50
100,000
60
100,000
ns
4
Row Cycle Time - Operation
tRC
80
90
ns
4
Row Cycle Time - Auto Refresh
tRFC
80
90
ns
4, 8
Last Data In to New Column Address Delay
tCDL
1
CLK
5
Last Data In to Row Precharge
tRDL
1
CLK
5
Last Data In to Burst Stop
tBDL
1
CLK
5
Column Address to Column Address Delay
tCCD
1
CLK
6
CAS latency = 3
2
CAS latency = 2
1
AC CHARACTERISTICS
OPERATING AC PARAMETERS
(VCC = 3.3V, TA = -40
°C to +85°C)
Clock Cycle Time
tCC
ns
1
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns, (trise 2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise & tfall are longer than 1ns, [(trise + tfall)/2]-1ns should be added to the parameter.
4. The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then rounding up to the
next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self refresh exit.
Number of Valid Output Data
ea
7
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