參數(shù)資料
型號(hào): EDI416S4030A10SI
英文描述: 1Mx 16 Bits x 4 Banks Synchronous DRAM(100MHz,1M x 16 位 x 4 組同步動(dòng)態(tài)RAM)
中文描述: 1Mx 16位× 4個(gè)銀行同步DRAM(100MHz的,100萬(wàn)× 16位× 4個(gè)組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 14/26頁(yè)
文件大?。?/td> 353K
代理商: EDI416S4030A10SI
21
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
FIG. 12 WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP CYCLE @
BURST LENGTH=FULL PAGE
RAS
CAS
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE
CAb
CAa
RAa
DQ
Precharge
(A-Bank)
Write
(A-Bank)
Burst Stop
Write
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
DON'T CARE
RAa
DAa0
DAa1
DAa2
DAa3
DAa4
DAb1
DAb0
DAb3
DAb2
DAb5
DAb4
Note 2
tRDL
tBDL
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM
at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when
asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
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