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| 型號(hào)： | EDI416S4030A10SI |
| 英文描述： | 1Mx 16 Bits x 4 Banks Synchronous DRAM(100MHz,1M x 16 位 x 4 組同步動(dòng)態(tài)RAM) |
| 中文描述： | 1Mx 16位× 4個(gè)銀行同步DRAM（100MHz的，100萬(wàn)× 16位× 4個(gè)組同步動(dòng)態(tài)RAM）的 |
| 文件頁(yè)數(shù)： | 2/26頁(yè) |
| 文件大小： | 353K |
| 代理商： | EDI416S4030A10SI |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
NOTES:
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to.
2. All Banks must be idle otherwise it is an illegal action.
3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4. The Current State refers only to one of the banks, if BA0, BA1 selects this bank then the action is illegal. If BA0, BA1 selects the bank not being referenced
by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
CURRENT STATE TRUTH TABLE (cont.)
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
L
H
BA
Row Address
Bank Activate
ILLEGAL
Refreshing
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
Burst Termination
No Operation; Idle after tRC
L
H
X
No Operation
No Operation; Idle after tRC
H
X
Device Deselect
No Operation; Idle after tRC
L
OP Code
Mode Register Set
ILLEGAL
L
H
X
Auto orSelf Refresh
ILLEGAL
L
H
L
X
Precharge
ILLEGAL
Mode Register
L
H
BA
Row Address
Bank Activate
ILLEGAL
Accessing
L
H
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
L
X
Burst Termination
ILLEGAL
L
H
X
No Operation
No Operation; Idle after two clock cycles
H
X
Device Deselect
No Operation; Idle after two clock cycles
Current State
Command
Action
Notes
CE
RAS
CAS
WE
BA
A11,
Description
A10/AP-A0
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| EDI416S4030A12SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1Mx16 Bits x 4 Banks Synchronous DRAM |
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| EDI441024C100BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
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