參數(shù)資料
型號(hào): EDI416S4030A10SI
英文描述: 1Mx 16 Bits x 4 Banks Synchronous DRAM(100MHz,1M x 16 位 x 4 組同步動(dòng)態(tài)RAM)
中文描述: 1Mx 16位× 4個(gè)銀行同步DRAM(100MHz的,100萬(wàn)× 16位× 4個(gè)組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 15/26頁(yè)
文件大小: 353K
代理商: EDI416S4030A10SI
22
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
FIG. 13 BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH=2
RAS
CAS
ADDR
BA
DQM
A10/AP
CKE
CLOCK
CE
CBc
CAd
RBb
CAa
RAa
CL = 2
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Write with
Auto Precharge
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
WE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
RAa
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
DON'T CARE
CAb
Note 2
RBb
RAc
CL = 3
DQ
QAb0
QAb1
DBc0
QAd0
QAd1
DAa0
Note 1
NOTES:
1. BRSW mode is enabled by setting As "High" at MRS (Mode Register Set). At the
BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS
should not be violated. Auto precharge is executed at the burst-end cycle, so in the case
of BRSW write command, the next cycle starts the precharge.
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